Fix resource issue with non inferring RAM (openrisc#66)

Introduced with commit 73bf629 (true_dpram: Use a single sequential block). Change to use 2 clocks to better match what xilinx expects when inferring true dual port RAM. Tested and works on quartus/altera/intel.
stffrdhrn · Jan 3, 2019 · 75a7b90 · 75a7b90
1 parent b3d3814
commit 75a7b90
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Showing 3 changed files with 17 additions and 7 deletions.
diff --git a/rtl/verilog/mor1kx_dmmu.v b/rtl/verilog/mor1kx_dmmu.v
@@ -419,10 +419,11 @@ for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : dtlb
        .dout_a (dtlb_match_dout[i]),
        .dout_b (dtlb_match_huge_dout[i]),
        // Inputs
-       .clk    (clk),
+       .clk_a  (clk),
        .addr_a (dtlb_match_addr),
        .we_a   (dtlb_match_we[i]),
        .din_a  (dtlb_match_din),
+       .clk_b  (clk),
        .addr_b (dtlb_match_huge_addr),
        .we_b   (dtlb_match_huge_we),
        .din_b  (dtlb_match_reload_din)
@@ -441,10 +442,11 @@ for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : dtlb
       .dout_a (dtlb_trans_dout[i]),
       .dout_b (dtlb_trans_huge_dout[i]),
       // Inputs
-      .clk    (clk),
+      .clk_a  (clk),
       .addr_a (dtlb_trans_addr),
       .we_a   (dtlb_trans_we[i]),
       .din_a  (dtlb_trans_din),
+      .clk_b  (clk),
       .addr_b (dtlb_trans_huge_addr),
       .we_b   (dtlb_trans_huge_we),
       .din_b  (dtlb_trans_reload_din)

diff --git a/rtl/verilog/mor1kx_immu.v b/rtl/verilog/mor1kx_immu.v
@@ -421,10 +421,11 @@ for (i = 0; i < OPTION_IMMU_WAYS; i=i+1) begin : itlb
        .dout_a (itlb_match_dout[i]),
        .dout_b (itlb_match_huge_dout[i]),
        // Inputs
-       .clk    (clk),
+       .clk_a  (clk),
        .addr_a (itlb_match_addr),
        .we_a   (itlb_match_we[i]),
        .din_a  (itlb_match_din),
+       .clk_b  (clk),
        .addr_b (itlb_match_huge_addr),
        .we_b   (itlb_match_huge_we),
        .din_b  (itlb_match_reload_din)
@@ -443,10 +444,11 @@ for (i = 0; i < OPTION_IMMU_WAYS; i=i+1) begin : itlb
       .dout_a (itlb_trans_dout[i]),
       .dout_b (itlb_trans_huge_dout[i]),
       // Inputs
-      .clk    (clk),
+      .clk_a  (clk),
       .addr_a (itlb_trans_addr),
       .we_a   (itlb_trans_we[i]),
       .din_a  (itlb_trans_din),
+      .clk_b  (clk),
       .addr_b (itlb_trans_huge_addr),
       .we_b   (itlb_trans_huge_we),
       .din_b  (itlb_trans_reload_din)

diff --git a/rtl/verilog/mor1kx_true_dpram_sclk.v b/rtl/verilog/mor1kx_true_dpram_sclk.v
@@ -4,7 +4,7 @@
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
- Description: True dual port ram with single clock
+ Description: True dual port ram with dual clock's
 
  Copyright (C) 2013 Stefan Kristiansson <[email protected]>
 
@@ -16,11 +16,15 @@ module mor1kx_true_dpram_sclk
     parameter DATA_WIDTH = 32
     )
    (
-    input                   clk,
+    /* Port A */
+    input                   clk_a,
     input [ADDR_WIDTH-1:0]  addr_a,
     input                   we_a,
     input [DATA_WIDTH-1:0]  din_a,
     output [DATA_WIDTH-1:0] dout_a,
+
+    /* Port B */
+    input                   clk_b,
     input [ADDR_WIDTH-1:0]  addr_b,
     input                   we_b,
     input [DATA_WIDTH-1:0]  din_b,
@@ -35,14 +39,16 @@ module mor1kx_true_dpram_sclk
    assign dout_a = rdata_a;
    assign dout_b = rdata_b;
 
-   always @(posedge clk) begin
+   always @(posedge clk_a) begin
       if (we_a) begin
          mem[addr_a] <= din_a;
          rdata_a <= din_a;
       end else begin
          rdata_a <= mem[addr_a];
       end
+   end
 
+   always @(posedge clk_b) begin
       if (we_b) begin
          mem[addr_b] <= din_b;
          rdata_b <= din_b;