Fix resource issue with non inferring RAM (openrisc#66)

Itroduced with commit 73bf629 (true_dpram: Use a single sequential block). Revert it back to fix the resource issue.
stffrdhrn · Jan 2, 2019 · 590e368 · 590e368
1 parent b3d3814
commit 590e368
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/rtl/verilog/mor1kx_true_dpram_sclk.v b/rtl/verilog/mor1kx_true_dpram_sclk.v
@@ -42,7 +42,11 @@ module mor1kx_true_dpram_sclk
       end else begin
          rdata_a <= mem[addr_a];
       end
+   end
 
+   /* Keep these two blocks separate even if Synopsys DC and Spyglass lint
+      complain.  Combining them causes quartus to fail to infer RAM blocks.  */
+   always @(posedge clk) begin
       if (we_b) begin
          mem[addr_b] <= din_b;
          rdata_b <= din_b;