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Merge pull request #67 from sifive/bump-all
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@terpstra
terpstra authored Jun 8, 2018
2 parents 66c9b73 + 50d2f7d commit 397c395
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Showing 12 changed files with 17 additions and 17 deletions.
4 changes: 2 additions & 2 deletions Makefile.e300artydevkit
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Expand Up @@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/xip
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
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4 changes: 2 additions & 2 deletions Makefile.u500polarfireevalkit
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Expand Up @@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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4 changes: 2 additions & 2 deletions Makefile.u500vc707devkit
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Expand Up @@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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4 changes: 2 additions & 2 deletions Makefile.u500vc707iofpga
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Expand Up @@ -11,8 +11,8 @@ export BOARD := vc707
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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4 changes: 2 additions & 2 deletions Makefile.veraiofpga
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Expand Up @@ -11,8 +11,8 @@ export BOARD := vera
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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2 changes: 1 addition & 1 deletion fpga-shells
Submodule fpga-shells updated 3 files
+4 −5 src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+1 −1 src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+23 −40 src/main/scala/ip/xilinx/Xilinx.scala
2 changes: 1 addition & 1 deletion rocket-chip
Submodule rocket-chip updated from 4ba8ac to 846425
2 changes: 1 addition & 1 deletion sifive-blocks
Submodule sifive-blocks updated 21 files
+11 −7 src/main/scala/devices/chiplink/ChipLink.scala
+1 −2 src/main/scala/devices/chiplink/RX.scala
+1 −1 src/main/scala/devices/chiplink/SinkD.scala
+1 −0 src/main/scala/devices/chiplink/SourceA.scala
+1 −0 src/main/scala/devices/chiplink/SourceB.scala
+1 −1 src/main/scala/devices/chiplink/SourceC.scala
+8 −7 src/main/scala/devices/chiplink/SourceD.scala
+0 −4 src/main/scala/devices/chiplink/TX.scala
+36 −19 src/main/scala/devices/gpio/GPIO.scala
+16 −6 src/main/scala/devices/i2c/I2C.scala
+5 −3 src/main/scala/devices/mockaon/MockAONPeriphery.scala
+38 −0 src/main/scala/devices/mockaon/RTC.scala
+27 −19 src/main/scala/devices/mockaon/WatchdogTimer.scala
+6 −2 src/main/scala/devices/msi/MSIMaster.scala
+31 −17 src/main/scala/devices/pwm/PWM.scala
+51 −30 src/main/scala/devices/spi/TLSPI.scala
+20 −11 src/main/scala/devices/spi/TLSPIFlash.scala
+30 −18 src/main/scala/devices/uart/UART.scala
+5 −4 src/main/scala/util/RegMapFIFO.scala
+19 −0 src/main/scala/util/SlaveRegIF.scala
+192 −45 src/main/scala/util/Timer.scala
2 changes: 1 addition & 1 deletion src/main/scala/unleashed/u500polarfireevalkit/Config.scala
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Expand Up @@ -47,7 +47,7 @@ class U500PolarFireEvalKitConfig extends Config(
case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
// case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
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2 changes: 1 addition & 1 deletion src/main/scala/unleashed/u500vc707devkit/Config.scala
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Expand Up @@ -44,7 +44,7 @@ class U500VC707DevKitConfig extends Config(
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
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2 changes: 1 addition & 1 deletion src/main/scala/unleashed/u500vcu118devkit/Config.scala
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Expand Up @@ -44,7 +44,7 @@ class U500VCU118DevKitConfig extends Config(
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVCU118MIGParams(address = Seq(AddressSet(0x80000000L,0x80000000L-1))) //2GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x80000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x80000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
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2 changes: 1 addition & 1 deletion src/main/scala/unleashed/u500vera/Config.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ class U500VeraConfig extends Config(
case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
// case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
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