fix for chipsalliance/firrtl#2095 and chipsalliance/chisel#1730

sequencer · Jul 13, 2021 · 40bfd71 · 40bfd71
1 parent 731a529
commit 40bfd71
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala b/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala
@@ -141,7 +141,7 @@ object IOCell {
     * @param name An optional name or name prefix to use for naming IO cells
     * @return A Seq of all generated IO cell instances
     */
-  val toSyncReset:  (Reset) => Bool = _.toBool
+  val toSyncReset:  (Reset) => Bool = _.asBool
   val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
   def generateFromSignal[T <: Data, R <: Reset](
     coreSignal:        T,

diff --git a/macros/src/main/scala/barstools/macros/MacroCompiler.scala b/macros/src/main/scala/barstools/macros/MacroCompiler.scala
@@ -8,7 +8,7 @@
 package barstools.macros
 
 import barstools.macros.Utils._
-import firrtl.Utils._
+import firrtl.Utils.{BoolType, one, zero}
 import firrtl.annotations._
 import firrtl.ir._
 import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation}

diff --git a/macros/src/main/scala/barstools/macros/SynFlops.scala b/macros/src/main/scala/barstools/macros/SynFlops.scala
@@ -3,7 +3,7 @@
 package barstools.macros
 
 import barstools.macros.Utils._
-import firrtl.Utils._
+import firrtl.Utils.{min, one, zero}
 import firrtl._
 import firrtl.ir._
 import firrtl.passes.MemPortUtils.memPortField