x64: Add memory operand support to EVEX instructions (bytecodeallianc…

…e#6416) * x64: Add memory operand support to EVEX instructions Currently load-sinking is enabled for EVEX instructions (aka AVX512 instructions) but the encoding of these instructions is a `todo!()` which can cause a panic for some wasms if the right features are enabled. This commit fills out the support for memory operands in the same manner as VEX-encoded instructions. The main stickler here was that EVEX instructions always use a scaled 8-bit offset which needed extra handling to ensure that the correct offset is emitted. * Pass scaling to `Imm` construction * Review comments * Fix tests * Fix evex benchmark
saulecabrera · May 24, 2023 · 797e769 · 797e769
1 parent afde47c
commit 797e769
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Showing 7 changed files with 506 additions and 108 deletions.
diff --git a/cranelift/codegen/benches/x64-evex-encoding.rs b/cranelift/codegen/benches/x64-evex-encoding.rs
@@ -14,12 +14,11 @@ mod x86 {
     fn x64_evex_encoding_benchmarks(c: &mut Criterion) {
         let mut group = c.benchmark_group("x64 EVEX encoding");
         let rax = Register::from(0);
-        let rdx = Register::from(2);
+        let rdx = 2;
 
         group.bench_function("EvexInstruction (builder pattern)", |b| {
-            let mut sink = vec![];
             b.iter(|| {
-                sink.clear();
+                let mut sink = cranelift_codegen::MachBuffer::new();
                 EvexInstruction::new()
                     .prefix(LegacyPrefixes::_66)
                     .map(OpcodeMap::_0F38)