[LLVM][XTHeadVector] support nvx1i1/nvx2i1/nvx4i1 operands for vector mask operations
#120
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imkiva
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vbool16/32/64_t for vector mask operations
imkiva
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vbool16/32/64_t for vector mask operationsnvx1i1/nvx2i1/nvx4i1 operands for vector mask operations
imkiva
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nvx1i1/nvx2i1/nvx4i1 operands for vector mask operationsnvx1i1/nvx2i1/nvx4i1 operands for vector mask operations
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Feb 24, 2025
…or mask operations (ruyisdk#120) * [LLVM][XTHeadVector] support `vbool16/32/64` for vector mask operations * [LLVM][XTHeadVector] correctly expand pseudos for `vmset/vmclr` * [LLVM][XTHeadVector] update corresponding tests * [LLVM][XTHeadVector] update tests for `vmsof/vmsbf/vmsif` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc`
imkiva
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Feb 26, 2025
…or mask operations (ruyisdk#120) * [LLVM][XTHeadVector] support `vbool16/32/64` for vector mask operations * [LLVM][XTHeadVector] correctly expand pseudos for `vmset/vmclr` * [LLVM][XTHeadVector] update corresponding tests * [LLVM][XTHeadVector] update tests for `vmsof/vmsbf/vmsif` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc` * [LLVM][XTHeadVector] update tests for `vmfirst/vmpopc`
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This PR fixed an issue introduced in #95 where the element size of
vbool16/32/64_tis computed from fractional LMUL, making it incompatible with XTHeadVector.This PR applies another strategy of setting LMUL and SEW when computing
<n> = SEW/LMULinvbool<n>_t:<n> = 1, 2, 4, 8, we assumeSEW = 8, and setLMUL = 8/4/2/1respectively. This is the same as the old behavior and mainline RVV implementation.<n> = 16, 32, 64, we assumeLMUL = 1, and setSEW = 16/32/64respectively. Thus no fractional LMUL is involved, and the generated code can pass MC validation.