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[Clang][XTHeadVector] Implement 14.12-14.15 `vmf{eq,ne,lt,le,gt,ge}/v…
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…fclass/vfmerge/vfmv.v` (#113)

* [Clang][XTHeadVector] Implement 14.12-14.15 `vmf{eq,ne,lt,le,gt,ge}/vfclass/vfmerge/vfmv.v`

* [Clang][XTHeadVector] Test 14.12-14.15 `vmf{eq,ne,lt,le,gt,ge}/vfclass/vfmerge/vfmv.v`

* [Clang][XTHeadVector] Implement wrappers 14.12-14.15 `vmf{eq,ne,lt,le,gt,ge}/vfclass/vfmerge/vfmv.v`
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@imkiva
imkiva authored May 20, 2024
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46 changes: 46 additions & 0 deletions clang/include/clang/Basic/riscv_vector_xtheadv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,11 @@ multiclass RVVFloatingWidenBinBuiltinSet
[["vv", "w", "wvv"],
["vf", "w", "wve"]]>;

multiclass RVVFloatingMaskOutBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "xfd",
[["vv", "vm", "mvv"],
["vf", "vm", "mve"]]>;

multiclass RVVSignedMaskOutBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "csil",
[["vv", "vm", "mvv"],
Expand Down Expand Up @@ -1737,6 +1742,47 @@ let UnMaskedPolicyScheme = HasPassthruOperand,
defm th_vfneg_v : RVVPseudoVFUnaryBuiltin<"th_vfsgnjn", "xfd">;
defm th_vfabs_v : RVVPseudoVFUnaryBuiltin<"th_vfsgnjx", "xfd">;

// 14.12. Vector Floating-Point Compare Instructions
let MaskedPolicyScheme = HasPassthruOperand,
HasTailPolicy = false in {
defm th_vmfeq : RVVFloatingMaskOutBuiltinSet;
defm th_vmfne : RVVFloatingMaskOutBuiltinSet;
defm th_vmflt : RVVFloatingMaskOutBuiltinSet;
defm th_vmfle : RVVFloatingMaskOutBuiltinSet;
defm th_vmfgt : RVVFloatingMaskOutBuiltinSet;
defm th_vmfge : RVVFloatingMaskOutBuiltinSet;
}

// 14.13. Vector Floating-Point Classify Instruction
let Name = "th_vfclass_v",
UnMaskedPolicyScheme = HasPassthruOperand,
MaskedPolicyScheme = HasPassthruOperand in
def th_vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;

// 14.14. Vector Floating-Point Merge Instructio
// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
let HasMasked = false,
UnMaskedPolicyScheme = HasPassthruOperand,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
// insert poison passthru
if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops.back()->getType()};
}] in {
defm th_vfmerge : RVVOutOp1BuiltinSet<"th_vfmerge", "xfd",
[["vfm", "v", "vvem"]]>;
}

// 14.15. Vector Floating-Point Move Instruction
let HasMasked = false,
UnMaskedPolicyScheme = HasPassthruOperand,
SupportOverloading = false,
MaskedPolicyScheme = NonePolicy,
OverloadedName = "th_vfmv_v" in
defm th_vfmv_v : RVVOutBuiltinSet<"th_vfmv_v_f", "xfd",
[["f", "v", "ve"]]>;

// 15. Vector Reduction Operations
// 15.1. Vector Single-Width Integer Reduction Instructions
let UnMaskedPolicyScheme = HasPassthruOperand,
Expand Down
336 changes: 336 additions & 0 deletions clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
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249 changes: 249 additions & 0 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating/thead/vfclass.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,249 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
// RUN: -target-feature +d -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

#include <riscv_vector.h>

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.th.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vfclass_v_u16m1(vfloat16m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m1(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.th.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vfclass_v_u16m2(vfloat16m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m2(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.th.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vfclass_v_u16m4(vfloat16m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m4(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.th.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vfclass_v_u16m8(vfloat16m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m8(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vfclass_v_u32m1(vfloat32m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m1(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vfclass_v_u32m2(vfloat32m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m2(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vfclass_v_u32m4(vfloat32m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m4(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.th.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vfclass_v_u32m8(vfloat32m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m8(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.th.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vfclass_v_u64m1(vfloat64m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m1(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.th.vfclass.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vfclass_v_u64m2(vfloat64m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m2(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.th.vfclass.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vfclass_v_u64m4(vfloat64m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m4(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.th.vfclass.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[OP1]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vfclass_v_u64m8(vfloat64m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m8(op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.th.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vfclass_v_u16m1_m(vbool16_t mask, vfloat16m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m1_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.th.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vfclass_v_u16m2_m(vbool8_t mask, vfloat16m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m2_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.th.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vfclass_v_u16m4_m(vbool4_t mask, vfloat16m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m4_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.th.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vfclass_v_u16m8_m(vbool2_t mask, vfloat16m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u16m8_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vfclass_v_u32m1_m(vbool32_t mask, vfloat32m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m1_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vfclass_v_u32m2_m(vbool16_t mask, vfloat32m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m2_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vfclass_v_u32m4_m(vbool8_t mask, vfloat32m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m4_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.th.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vfclass_v_u32m8_m(vbool4_t mask, vfloat32m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u32m8_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.th.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vfclass_v_u64m1_m(vbool64_t mask, vfloat64m1_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m1_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.th.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vfclass_v_u64m2_m(vbool32_t mask, vfloat64m2_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m2_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.th.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vfclass_v_u64m4_m(vbool16_t mask, vfloat64m4_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m4_m(mask, op1, vl);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.th.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vfclass_v_u64m8_m(vbool8_t mask, vfloat64m8_t op1, size_t vl) {
return __riscv_th_vfclass_v_u64m8_m(mask, op1, vl);
}

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