updated cargo.toml to deal with yanked riscv 0.9.0, see esp-rs/esp-ha…

…l#349

Cargo.toml

@@ -27,10 +27,10 @@ opt-level = "s"
 # panic-halt = "0.2"
 embedded-hal = "0.2"
 critical-section = "1.1.1"
-esp-hal-common = { git = "https://github.com/esp-rs/esp-hal", features = ["esp32c3"], rev = "4d036c3" }
-esp32c3-hal = { git = "https://github.com/esp-rs/esp-hal", features = ["direct-boot"], rev = "4d036c3" }
+esp-hal-common = { git = "https://github.com/esp-rs/esp-hal", features = ["esp32c3"], rev = "d29c4b1" }
+esp32c3-hal = { git = "https://github.com/esp-rs/esp-hal", features = ["direct-boot"], rev = "d29c4b1" }
 riscv = "0.10.0"
-riscv-rt = "0.10.0"
+riscv-rt = "0.11.0"
 nb = "1.0"
 bare-metal = "1.0.0"
 esp-alloc = { version = "0.1.0", features = ["oom-handler"] }