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Always specify llvm_abiname for RISC-V targets #131807

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merged 1 commit into from
Oct 22, 2024
Merged

Always specify llvm_abiname for RISC-V targets #131807

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32i_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32im_risc0_zkvm_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,

features: "+m".into(),
llvm_abiname: "ilp32".into(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32im_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+m,+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32ima_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imac_esp_espidf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,

features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imac_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imac_unknown_nuttx_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imac_unknown_xous_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imc_esp_espidf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,

features: "+m,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imc_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+m,+c,+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
Expand Down
1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imc_unknown_nuttx_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv64imac_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+c".into(),
llvm_abiname: "lp64".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/riscv64imac_unknown_nuttx_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+c".into(),
llvm_abiname: "lp64".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),
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11 changes: 11 additions & 0 deletions compiler/rustc_target/src/spec/tests/tests_impl.rs
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Expand Up @@ -152,6 +152,17 @@ impl Target {
if self.crt_static_default || self.crt_static_allows_dylibs {
assert!(self.crt_static_respected);
}

// Check that RISC-V targets always specify which ABI they use.
match &*self.arch {
"riscv32" => {
assert_matches!(&*self.llvm_abiname, "ilp32" | "ilp32f" | "ilp32d" | "ilp32e")
}
"riscv64" => {
assert_matches!(&*self.llvm_abiname, "lp64" | "lp64f" | "lp64d" | "lp64q")
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What about lp64e?

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we currently don't support any rv64e targets, and we don't really (intentionally) support "this can have one of multiple ABIs" target tuples. we'll need to fix this when we cross that bridge though, so if you want to PR to fix it now, happy to take that on.

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more explicitly: r? me and I'll sign off on it.

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I took the list of ABIs from the RISC-V ABIs Specification: lp64e is not currently mentioned anywhere in that document as it's still waiting for a 2-year-old PR to be reviewed and merged.

}
_ => {}
}
}

// Add your target to the whitelist if it has `std` library
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46 changes: 46 additions & 0 deletions tests/assembly/riscv-soft-abi-with-float-features.rs
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@@ -0,0 +1,46 @@
//@ assembly-output: emit-asm
//@ compile-flags: --target riscv64imac-unknown-none-elf -Ctarget-feature=+f,+d
//@ needs-llvm-components: riscv

#![feature(no_core, lang_items, f16)]
#![crate_type = "lib"]
#![no_core]

#[lang = "sized"]
trait Sized {}

#[lang = "copy"]
trait Copy {}

impl Copy for f16 {}
impl Copy for f32 {}
impl Copy for f64 {}

// This test checks that the floats are all returned in `a0` as required by the `lp64` ABI.

// CHECK-LABEL: read_f16
#[no_mangle]
pub extern "C" fn read_f16(x: &f16) -> f16 {
// CHECK: lh a0, 0(a0)
// CHECK-NEXT: lui a1, 1048560
// CHECK-NEXT: or a0, a0, a1
// CHECK-NEXT: ret
*x
}

// CHECK-LABEL: read_f32
#[no_mangle]
pub extern "C" fn read_f32(x: &f32) -> f32 {
// CHECK: flw fa5, 0(a0)
// CHECK-NEXT: fmv.x.w a0, fa5
// CHECK-NEXT: ret
*x
}

// CHECK-LABEL: read_f64
#[no_mangle]
pub extern "C" fn read_f64(x: &f64) -> f64 {
// CHECK: ld a0, 0(a0)
// CHECK-NEXT: ret
*x
}
2 changes: 1 addition & 1 deletion tests/codegen/riscv-target-abi.rs
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Expand Up @@ -10,7 +10,7 @@

//@[riscv32imac] compile-flags: --target=riscv32imac-unknown-none-elf
//@[riscv32imac] needs-llvm-components: riscv
// riscv32imac-NOT: !"target-abi"
// riscv32imac: !{i32 1, !"target-abi", !"ilp32"}

#![feature(no_core, lang_items)]
#![crate_type = "lib"]
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