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Promote tier 3 riscv32 bare metal targets to tier 2 #701
Comments
This issue is not meant to be used for technical discussion. There is a Zulip stream for that. Use this issue to leave procedural comments, such as volunteering to review, indicating that you second the proposal (or third, etc), or raising a concern that you would like to be addressed. cc @rust-lang/compiler @rust-lang/compiler-contributors |
@rustbot second |
This leads to a 404, at least for me. Is the URL correct? |
Ah, I guess the Github team itself is not public. The team is listed upstream here: https://github.com/rust-lang/team/blob/master/teams/wg-embedded-riscv.toml. I've updated the link in the original post. |
@rustbot label -final-comment-period +major-change-accepted |
Promote `riscv32{im|imafc}` targets to tier 2 Pending the approval of [the MCP](rust-lang/compiler-team#701).
Promote `riscv32{im|imafc}` targets to tier 2 Pending the approval of [the MCP](rust-lang/compiler-team#701).
Promote `riscv32{im|imafc}` targets to tier 2 Pending the approval of [the MCP](rust-lang/compiler-team#701).
Rollup merge of rust-lang#118704 - esp-rs:rv32-tier-2, r=davidtwco Promote `riscv32{im|imafc}` targets to tier 2 Pending the approval of [the MCP](rust-lang/compiler-team#701).
Promote `riscv32{im|imafc}` targets to tier 2 Pending the approval of [the MCP](rust-lang/compiler-team#701).
Proposal
I would like to propose promoting the remaining RISC-V 32bit bare metal targets,
riscv32im-unknown-none-elf
&riscv32imafc-unknown-none-elf
to tier 2.Tier 2 target requirements
RISC-V is an open specification, used and accessible to anyone including individuals.
This rust-embedded working group's RISCV team will maintain these targets.
I don't forsee this being an issue, the RISCV team will ensure we avoid undue burden for the general Rust community.
There are links to resources we maintain in the re wg org in the platform support document.
Documented in the platform support document.
New target features in RISCV can drastically change the capability of a CPU, hence the need for a separate target to support different variants. We aim to support any ratified RISCV extensions.
core
is fully implemented.RISCV is a well-established and well-maintained LLVM backend. To the best of my knowledge, the backend won't cause the generated code to have undefined behaviour.
The C calling convention is supported by RISCV.
For the last 4-5 years many of these RISCV targets have been building in CI without any known issues.
Not applicable, in the future we may wish to add qemu tests but this is out of scope for now.
To the best of my knowledge, this will not induce a burden on the current CI infra.
Cross-compilation is supported and documented in the platform support document.
There are no additional license issues to worry about.
The RISCV team agrees not to do this.
The RISCV team will fix any issues in a timely manner.
Mentors or Reviewers
@davidtwco
Process
The main points of the Major Change Process are as follows:
@rustbot second
.-C flag
, then full team check-off is required.@rfcbot fcp merge
on either the MCP or the PR.You can read more about Major Change Proposals on forge.
Comments
This issue is not meant to be used for technical discussion. There is a Zulip stream for that. Use this issue to leave procedural comments, such as volunteering to review, indicating that you second the proposal (or third, etc), or raising a concern that you would like to be addressed.
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