Skip to content

Commit

Permalink
scale up benchmarks
Browse files Browse the repository at this point in the history
  • Loading branch information
romnn committed Nov 16, 2023
1 parent c0d9858 commit b0aa981
Show file tree
Hide file tree
Showing 21 changed files with 10,181 additions and 3,509 deletions.
351 changes: 15 additions & 336 deletions Cargo.lock

Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions WIP.md
Original file line number Diff line number Diff line change
Expand Up @@ -67,17 +67,10 @@ The Maxwell/Pascal L1 data cache had similar tag stage performance but local and

- TODO:

- overall results in parallel table
- parallel remove .0 where possible
- DONE: bold font for best results in parallel table
- DONE: remove parallel execution from exec driven simulate (only baseline)
- DONE: fix parallel plot table (multiple kernel launch ids)

- DONE: compute blocks per sm metric for parallel, maybe we just need to scale up the workloads
- validate: add remote connection to das5 and das6

- make the basic plots look good for pascal pchase and write it down
- run the same for older fermi or maxwell gpu on das5 and write it down
- GIVE UP: have another go at ampere

- plot: compare mem only simulation and trace reconstruction error
- plot: compute overall correlations for all metrics
Expand All @@ -88,6 +81,13 @@ The Maxwell/Pascal L1 data cache had similar tag stage performance but local and
- check if any line ever has different hit_cluster, otherwise makes no sense
- this prob wont be interesting for l1, but maybe l2?

- DONE: overall results in parallel table
- GIVE UP: have another go at ampere
- DONE: parallel remove .0 where possible
- DONE: bold font for best results in parallel table
- DONE: remove parallel execution from exec driven simulate (only baseline)
- DONE: fix parallel plot table (multiple kernel launch ids)
- DONE: compute blocks per sm metric for parallel, maybe we just need to scale up the workloads
- DONE: simulator: l1 latency should only affect HITS ==> l1 return queue
- GIVE UP: research: try to understand the l1 tex cache hit rate nvprof metric
- DONE: connect to das6
Expand Down
10 changes: 7 additions & 3 deletions gpucachesim/benchmarks.py
Original file line number Diff line number Diff line change
Expand Up @@ -303,12 +303,16 @@ def construct_playground_simulate_target_config(self, node):


class Benchmarks:
path: Path
config: Config

def __init__(self, path: os.PathLike) -> None:
def __init__(self, path: typing.Optional[os.PathLike]) -> None:
"""load the materialized benchmark config"""

with open(path or DEFAULT_BENCH_FILE, "rb") as f:
if path is None:
self.path = DEFAULT_BENCH_FILE
else:
self.path = Path(path)
with open(self.path, "rb") as f:
benchmarks = yaml.load(f, Loader=BenchmarkLoader)

self.config = benchmarks["config"]
Expand Down
Loading

0 comments on commit b0aa981

Please sign in to comment.