Add tests for SimdInt::{load_extend_i8, load_interleave_i8, sum}

Makefile

@@ -59,11 +59,19 @@ wasm-nosimd:
 .PHONY: wasm-all
 wasm-all: wasm wasm-nosimd
 
+# WASM tests run with `--nocapture` as otherwise assertion failure panic messages
+# are not printed if a test assert fails.
 .PHONY: wasm-tests
 wasm-tests:
 	rm -f target/wasm32-wasi/debug/deps/rten-*.wasm
 	RUSTFLAGS="-C target-feature=+simd128" cargo build --target wasm32-wasip1 --tests -p rten
-	wasmtime --dir . target/wasm32-wasip1/debug/deps/rten-*.wasm
+	wasmtime --dir . target/wasm32-wasip1/debug/deps/rten-*.wasm --nocapture
+
+.PHONY: wasm-tests
+wasm-tests-simd:
+	rm -f target/wasm32-wasi/debug/deps/rten_simd-*.wasm
+	RUSTFLAGS="-C target-feature=+simd128" cargo build --target wasm32-wasip1 --tests -p rten-simd
+	wasmtime --dir . target/wasm32-wasip1/debug/deps/rten_simd-*.wasm --nocapture
 
 src/schema_generated.rs: src/schema.fbs
 	flatc -o src/ --rust src/schema.fbs

rten-simd/src/arch/wasm.rs

@@ -305,3 +305,10 @@ impl SimdFloat for v128f {
         f32x4_extract_lane::<0>(sum)
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use crate::vec::tests::test_simdint;
+
+    test_simdint!(v128i_simdint, crate::arch::wasm::v128i);
+}

rten-simd/src/arch/x86_64.rs

@@ -743,3 +743,13 @@ impl SimdFloat for __m512 {
         _mm512_reduce_add_ps(self)
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use crate::vec::tests::test_simdint;
+
+    test_simdint!(avx2_simdint, core::arch::x86_64::__m256i);
+
+    #[cfg(feature = "avx512")]
+    test_simdint!(avx512_simdint, core::arch::x86_64::__m512i);
+}

rten-simd/src/vec.rs

@@ -352,3 +352,72 @@ pub trait SimdFloat: Simd<Elem = f32> {
         Self::splat(reduced)
     }
 }
+
+#[cfg(test)]
+pub mod tests {
+    /// Generate tests for a `SimdInt` implementation.
+    macro_rules! test_simdint {
+        ($modname:ident, $type_import_path:ty) => {
+            mod $modname {
+                use crate::vec::{Simd, SimdInt};
+                use $type_import_path as SimdVec;
+
+                const LEN: usize = <SimdVec as Simd>::LEN;
+
+                #[test]
+                fn test_load_extend_i8() {
+                    let src: Vec<i8> = (0..).take(LEN).collect();
+                    let vec = unsafe { <SimdVec as SimdInt>::load_extend_i8(src.as_ptr()) };
+                    let actual = unsafe { vec.to_array() };
+                    let expected: Vec<_> = src.iter().map(|x| *x as i32).collect();
+                    assert_eq!(actual.as_ref(), expected);
+                }
+
+                #[test]
+                fn test_load_interleave_i8() {
+                    let group_step = 5;
+                    let a: Vec<_> = (0..).step_by(group_step).take(LEN).collect();
+                    let b: Vec<_> = (1..).step_by(group_step).take(LEN).collect();
+                    let c: Vec<_> = (2..).step_by(group_step).take(LEN).collect();
+                    let d: Vec<_> = (3..).step_by(group_step).take(LEN).collect();
+
+                    let mut expected = Vec::new();
+                    for step in 0..LEN {
+                        let base = step * group_step;
+                        for i in 0..4 {
+                            expected.push((base + i) as i8);
+                        }
+                    }
+
+                    let vec = unsafe {
+                        <SimdVec as SimdInt>::load_interleave_i8(
+                            a.as_ptr(),
+                            b.as_ptr(),
+                            c.as_ptr(),
+                            d.as_ptr(),
+                        )
+                    };
+                    let actual = unsafe { vec.to_array() };
+                    let actual: Vec<i8> = actual
+                        .as_ref()
+                        .iter()
+                        .flat_map(|x| x.to_le_bytes().map(|b| b as i8))
+                        .collect();
+
+                    assert_eq!(actual.as_ref(), expected);
+                }
+
+                #[test]
+                fn test_sum() {
+                    let src: Vec<i32> = (0..).take(LEN).collect();
+                    let vec = unsafe { <SimdVec as Simd>::load(src.as_ptr()) };
+                    let actual = unsafe { vec.sum() };
+                    let expected: i32 = src.iter().sum();
+                    assert_eq!(actual, expected);
+                }
+            }
+        };
+    }
+
+    pub(crate) use test_simdint;
+}