AIA: Permit supervisor-level interrupts even while corresponding bits…

… in mideleg remain 0s (interrupt filtering)

The modification is backward compatible because mvien is implicitly 0
without AIA.

riscv/processor.cc

@@ -906,8 +906,10 @@ reg_t processor_t::select_an_interrupt_with_default_priority(reg_t enabled_inter
 
 void processor_t::take_interrupt(reg_t pending_interrupts)
 {
+  const reg_t s_pending_interrupts = state.nonvirtual_sip->read() & state.nonvirtual_sie->read();
+
   // Do nothing if no pending interrupts
-  if (!pending_interrupts) {
+  if (!pending_interrupts && !s_pending_interrupts) {
     return;
   }
 
@@ -923,7 +925,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts)
     const reg_t deleg_to_hs = state.mideleg->read() & ~state.hideleg->read();
     const reg_t sie = get_field(state.sstatus->read(), MSTATUS_SIE);
     const reg_t hs_enabled = state.v || state.prv < PRV_S || (state.prv == PRV_S && sie);
-    enabled_interrupts = pending_interrupts & deleg_to_hs & -hs_enabled;
+    enabled_interrupts = s_pending_interrupts & deleg_to_hs & -hs_enabled;
     if (state.v && enabled_interrupts == 0) {
       // VS-ints have least priority and can only be taken with virt enabled
       const reg_t deleg_to_vs = state.hideleg->read();