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target: convert 'unsigned' to 'unsigned int'
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Conversion done with
	checkpatch --fix-inplace -types UNSPECIFIED_INT

Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).

Use Checkpatch-ignore below for the function pointers in the file
'armv7a_cache_l2x.h' that do not assign the identifier names to
the function arguments.
Most of these struct are unused and should be fixed or dropped.

Checkpatch-ignore: FUNCTION_ARGUMENTS

Change-Id: I8f27e68eb3502e431c1ba801b362358105f9f2dc
Signed-off-by: Antonio Borneo <[email protected]>
Reviewed-on: https://review.openocd.org/c/openocd/+/8480
Tested-by: jenkins
Reviewed-by: zapb <[email protected]>
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@borneoa
borneoa committed Oct 5, 2024
1 parent 2ad48b7 commit e72733d
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Showing 45 changed files with 248 additions and 246 deletions.
10 changes: 5 additions & 5 deletions src/target/adi_v5_jtag.c
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Original file line number Diff line number Diff line change
Expand Up @@ -736,7 +736,7 @@ static int jtag_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
return retval;
}

static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data)
{
int retval = jtag_limit_queue_size(dap);
Expand All @@ -749,7 +749,7 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
return retval;
}

static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
int retval = jtag_limit_queue_size(dap);
Expand All @@ -763,7 +763,7 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
}

/** Select the AP register bank */
static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned int reg)
{
int retval;
struct adiv5_dap *dap = ap->dap;
Expand Down Expand Up @@ -818,7 +818,7 @@ static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
return ERROR_OK;
}

static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data)
{
int retval = jtag_limit_queue_size(ap->dap);
Expand All @@ -840,7 +840,7 @@ static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
return retval;
}

static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
uint32_t data)
{
int retval = jtag_limit_queue_size(ap->dap);
Expand Down
10 changes: 5 additions & 5 deletions src/target/adi_v5_swd.c
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Original file line number Diff line number Diff line change
Expand Up @@ -485,7 +485,7 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
return check_sync(dap);
}

static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data)
{
int retval = swd_check_reconnect(dap);
Expand All @@ -499,7 +499,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
return swd_queue_dp_read_inner(dap, reg, data);
}

static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
Expand All @@ -517,7 +517,7 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
}

/** Select the AP register bank */
static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned int reg)
{
int retval;
struct adiv5_dap *dap = ap->dap;
Expand Down Expand Up @@ -567,7 +567,7 @@ static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
return ERROR_OK;
}

static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data)
{
struct adiv5_dap *dap = ap->dap;
Expand All @@ -592,7 +592,7 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
return check_sync(dap);
}

static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
uint32_t data)
{
struct adiv5_dap *dap = ap->dap;
Expand Down
4 changes: 2 additions & 2 deletions src/target/arc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -516,7 +516,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
unsigned long i = 0;
struct reg_cache *reg_cache = target->reg_cache;
while (reg_cache) {
for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
for (unsigned int j = 0; j < reg_cache->num_regs; j++, i++)
(*reg_list)[i] = &reg_cache->reg_list[j];
reg_cache = reg_cache->next;
}
Expand All @@ -527,7 +527,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
unsigned long gdb_reg_number = 0;
struct reg_cache *reg_cache = target->reg_cache;
while (reg_cache) {
for (unsigned j = 0;
for (unsigned int j = 0;
j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
j++) {
if (reg_cache->reg_list[j].exist) {
Expand Down
8 changes: 4 additions & 4 deletions src/target/arm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -143,8 +143,8 @@ enum {
ARM_VFP_V3_FPSCR,
};

const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
const char *arm_mode_name(unsigned int psr_mode);
bool is_arm_mode(unsigned int psr_mode);

/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
enum arm_state {
Expand Down Expand Up @@ -325,7 +325,7 @@ int arm_blank_check_memory(struct target *target,
struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);

void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
struct reg *arm_reg_current(struct arm *arm, unsigned int regnum);
struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum);

#endif /* OPENOCD_TARGET_ARM_H */
2 changes: 1 addition & 1 deletion src/target/arm11.c
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Original file line number Diff line number Diff line change
Expand Up @@ -478,7 +478,7 @@ static int arm11_resume(struct target *target, int current,
/* activate all breakpoints */
if (true) {
struct breakpoint *bp;
unsigned brp_num = 0;
unsigned int brp_num = 0;

for (bp = target->breakpoints; bp; bp = bp->next) {
struct arm11_sc7_action brp[2];
Expand Down
2 changes: 1 addition & 1 deletion src/target/arm11.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ struct arm11_common {
/** Debug module state. */
struct arm_dpm dpm;
struct arm11_sc7_action *bpwp_actions;
unsigned bpwp_n;
unsigned int bpwp_n;

size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */
Expand Down
10 changes: 5 additions & 5 deletions src/target/arm11_dbgtap.c
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Original file line number Diff line number Diff line change
Expand Up @@ -567,8 +567,8 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
chain5_fields[2].in_value = NULL;

uint8_t *readies;
unsigned readies_num = count;
unsigned bytes = sizeof(*readies)*readies_num;
unsigned int readies_num = count;
unsigned int bytes = sizeof(*readies) * readies_num;

readies = malloc(bytes);
if (!readies) {
Expand All @@ -592,7 +592,7 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,

int retval = jtag_execute_queue();
if (retval == ERROR_OK) {
unsigned error_count = 0;
unsigned int error_count = 0;

for (size_t i = 0; i < readies_num; i++) {
if (readies[i] != 1)
Expand Down Expand Up @@ -1042,7 +1042,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
* and watchpoint operations instead of running them right away. Since we
* pre-allocated our vector, we don't need to worry about space.
*/
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
uint32_t addr, uint32_t control)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
Expand Down Expand Up @@ -1079,7 +1079,7 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
return ERROR_OK;
}

static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
struct arm11_sc7_action *action;
Expand Down
6 changes: 3 additions & 3 deletions src/target/arm9tdmi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -821,9 +821,9 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
else if (strcmp(CMD_ARGV[0], "none") == 0) {
/* do nothing */
} else {
for (unsigned i = 0; i < CMD_ARGC; i++) {
for (unsigned int i = 0; i < CMD_ARGC; i++) {
/* go through list of vectors */
unsigned j;
unsigned int j;
for (j = 0; arm9tdmi_vectors[j].name; j++) {
if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) {
vector_catch_value |= arm9tdmi_vectors[j].value;
Expand All @@ -850,7 +850,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
}

/* output current settings */
for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
for (unsigned int i = 0; arm9tdmi_vectors[i].name; i++) {
command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name,
(vector_catch_value & arm9tdmi_vectors[i].value)
? "catch" : "don't catch");
Expand Down
20 changes: 10 additions & 10 deletions src/target/arm_adi_v5.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -454,17 +454,17 @@ struct dap_ops {
int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);

/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data);
/** DP register write. */
int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
int (*queue_dp_write)(struct adiv5_dap *dap, unsigned int reg,
uint32_t data);

/** AP register read. */
int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
int (*queue_ap_read)(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data);
/** AP register write. */
int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
int (*queue_ap_write)(struct adiv5_ap *ap, unsigned int reg,
uint32_t data);

/** AP operation abort. */
Expand Down Expand Up @@ -553,7 +553,7 @@ static inline int dap_send_sequence(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_dp_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
unsigned int reg, uint32_t *data)
{
assert(dap->ops);
return dap->ops->queue_dp_read(dap, reg, data);
Expand All @@ -571,7 +571,7 @@ static inline int dap_queue_dp_read(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_dp_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
unsigned int reg, uint32_t data)
{
assert(dap->ops);
return dap->ops->queue_dp_write(dap, reg, data);
Expand All @@ -588,7 +588,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_read(struct adiv5_ap *ap,
unsigned reg, uint32_t *data)
unsigned int reg, uint32_t *data)
{
assert(ap->dap->ops);
if (ap->refcount == 0) {
Expand All @@ -608,7 +608,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_write(struct adiv5_ap *ap,
unsigned reg, uint32_t data)
unsigned int reg, uint32_t data)
{
assert(ap->dap->ops);
if (ap->refcount == 0) {
Expand Down Expand Up @@ -659,7 +659,7 @@ static inline int dap_sync(struct adiv5_dap *dap)
return ERROR_OK;
}

static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned int reg,
uint32_t *value)
{
int retval;
Expand All @@ -671,7 +671,7 @@ static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
return dap_run(dap);
}

static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned int reg,
uint32_t mask, uint32_t value, int timeout)
{
assert(timeout > 0);
Expand Down
20 changes: 10 additions & 10 deletions src/target/arm_disassembler.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,7 @@ static int evaluate_pld(uint32_t opcode,
if ((opcode & 0x0d30f000) == 0x0510f000) {
uint8_t rn;
uint8_t u;
unsigned offset;
unsigned int offset;

instruction->type = ARM_PLD;
rn = (opcode & 0xf0000) >> 16;
Expand Down Expand Up @@ -701,9 +701,9 @@ static int evaluate_load_store(uint32_t opcode,

static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
{
unsigned rm = (opcode >> 0) & 0xf;
unsigned rd = (opcode >> 12) & 0xf;
unsigned rn = (opcode >> 16) & 0xf;
unsigned int rm = (opcode >> 0) & 0xf;
unsigned int rd = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 16) & 0xf;
char *type, *rot;

switch ((opcode >> 24) & 0x3) {
Expand Down Expand Up @@ -892,7 +892,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,

/* multiplies */
if ((opcode & 0x01f00080) == 0x01000000) {
unsigned rn = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 12) & 0xf;

if (rn != 0xf)
sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
Expand Down Expand Up @@ -925,7 +925,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
return ERROR_OK;
}
if ((opcode & 0x01f00000) == 0x01500000) {
unsigned rn = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 12) & 0xf;

switch (opcode & 0xc0) {
case 3:
Expand Down Expand Up @@ -1001,8 +1001,8 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
return ERROR_OK;
}
if (mnemonic) {
unsigned rm = (opcode >> 0) & 0xf;
unsigned rd = (opcode >> 12) & 0xf;
unsigned int rm = (opcode >> 0) & 0xf;
unsigned int rd = (opcode >> 12) & 0xf;

sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
return ERROR_OK;
Expand Down Expand Up @@ -2747,7 +2747,7 @@ static int evaluate_cond_branch_thumb(uint16_t opcode,
static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction)
{
unsigned offset;
unsigned int offset;

/* added in Thumb2 */
offset = (opcode >> 3) & 0x1f;
Expand Down Expand Up @@ -2858,7 +2858,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction)
{
unsigned cond = (opcode >> 4) & 0x0f;
unsigned int cond = (opcode >> 4) & 0x0f;
char *x = "", *y = "", *z = "";

if (opcode & 0x01)
Expand Down
2 changes: 1 addition & 1 deletion src/target/arm_disassembler.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -171,7 +171,7 @@ struct arm_instruction {
uint32_t opcode;

/* return value ... Thumb-2 sizes vary */
unsigned instruction_size;
unsigned int instruction_size;

union {
struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
Expand Down
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