This is a simulator of a MIPS microprocesor built using plain excel formulas. This design is ment for educational purposes only. The implemented MIPS version is the following non-pipelined version
- Modules
- Instruction set
- R-Type
- I-Type
- IO
- Branch
- Jump
- Use of compiler
- Example program
The microprocesor is divided in the following modules:
- PC (Program Counter)
- Instruction Memory
- Register Bank
- ALU (Arithmetic Logic Unit)
- Control Unit
- Data Memory
Each module of the microprocesor is implemented on a different excel page, organized as follows: A VB macro which updates the clock every second can be triggered by hitting the button on the PC page.
Type | Name | Arguments | Notes |
R-Type | add | rs, rt, rd | |
sub | rs, rt, rd | ||
mult | rs, rt, rd | ||
div | rs, rt, rd | ||
mod | rs, rt, rd | ||
and | rs, rt, rd | ||
or | rs, rt, rd | ||
slt | rs, rt, rd | ||
move | rt, rd | Pseudo-instruction (provided by compiler) | |
I-Type | addi | rs, rt, inmediate | |
subi | rs, rt, inmediate | ||
multi | rs, rt, inmediate | ||
divi | rs, rt, inmediate | ||
modi | rs, rt, inmediate | ||
andi | rs, rt, inmediate | ||
ori | rs, rt, inmediate | ||
slti | rs, rt, inmediate | ||
inc | rs | Pseudo-instruction (provided by compiler) | |
dec | rs | Pseudo-instruction (provided by compiler) | |
IO | lw | rs, rt, offset | |
sw | rs, rt, offset | ||
Branch | beq | rs, rt, address offset | |
Jump | j | address | |
jr | rs | ||
jal | address | Pseudo-instruction (provided by compiler) |
The python script compiler.py
compiles all assembly files in the ./src/
folder and stores a compiled binary version at ./bin/
as well as a binary version at ./dec/
. You can copy this last binary version and paste it at the instrucion memory.
The compiler can be invoked just by using python compiler.py
. No external libraries are required.
Example of an assembly program to compute
; Compute e^x where x is the first number in memory, using Taylor series
; The second number in memory is used as the number of iterations to perform
; Load data
LW $0 $s0 0 ; x
LW $0 $s1 1 ; n
MOVE $0 $s2 ; result
MOVE $0 $s3 ; i
INC $s1
@LoopBegin
BEQ $s3 $s1 @LoopEnd
; Call power
MOVE $s0 $a0
MOVE $s3 $a1
JAL @power
MOVE $v0 $s4
; Call factorial
MOVE $s3 $a0
JAL @factorial
MOVE $v0 $s5
; Update value
DIV $s4 $s5 $s6
ADD $s2 $s6 $s2
INC $s3
J @LoopBegin
@LoopEnd
; Store result
SW $0 $s2 2
J @End
; Power function
@power
LOADI $v0 1
@LoopBegin1
BEQ $a1 $0 @LoopEnd1
MULT $a0 $v0 $v0
DEC $a1
J @LoopBegin1
@LoopEnd1
JR $ra
; Factorial function
@factorial
LOADI $v0 1
@LoopBegin2
BEQ $a0 $0 @LoopEnd2
MULT $a0 $v0 $v0
DEC $a0
J @LoopBegin2
@LoopEnd2
JR $ra
@End