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    221 repositories

    • cace

      Public
      Circuit Automatic Characterization Engine
      Python
      •
      Apache License 2.0
      •7•47•25•3•Updated Feb 7, 2025Feb 7, 2025

    • caravel

      Public
      Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
      magicyosyscaravelpicorv32openroadvexriscvopenramsky130
      Verilog
      •
      Apache License 2.0
      •69•308•95•8•Updated Feb 7, 2025Feb 7, 2025

    • openframe_user_project

      Public template
      Example digital project for the Efabless Caravel "openframe" harness
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 7, 2025Feb 7, 2025

    • mpw_precheck

      Public
      Python
      •
      Apache License 2.0
      •24•36•40•6•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_mini

      Public template
      Verilog
      •
      Apache License 2.0
      •1•3•2•2•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_project_analog

      Public template
      Verilog
      •
      Apache License 2.0
      •89•45•6•2•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_project

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •334•190•85•23•Updated Feb 7, 2025Feb 7, 2025

    • EF_WDT32

      Public
      A simple WatchDog Timer (WDT)
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_UART

      Public
      Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
      Verilog
      •
      Apache License 2.0
      •3•8•11•1•Updated Feb 6, 2025Feb 6, 2025

    • caravel_user_UART

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      0•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •44•262•86•11•Updated Feb 6, 2025Feb 6, 2025

    • caravel_user_sram

      Public
      Verilog
      •
      Apache License 2.0
      •0•4•7•1•Updated Feb 6, 2025Feb 6, 2025

    • EF_SHA256

      Public
      Verilog
      •0•0•2•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_AES

      Public
      Verilog
      •0•0•1•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_GPIO8

      Public
      A generic 8-bit General Purpose I/O (GPIO) Peripheral
      Verilog
      •
      Apache License 2.0
      •1•1•1•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_SPI

      Public
      Verilog
      •0•0•5•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_I2S

      Public
      Two-wire I2S synchronous serial interface, compatible with I2S specification.
      Verilog
      •
      Apache License 2.0
      •0•0•6•2•Updated Feb 6, 2025Feb 6, 2025

    • EF_TMR32

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•2•0•Updated Feb 6, 2025Feb 6, 2025

    • BusWrap

      Public
      Python
      •0•5•6•0•Updated Feb 6, 2025Feb 6, 2025

    • Frigate-OS

      Public
      Verilog
      •0•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • caravel_SI_testing

      Public
      C
      •1•2•3•5•Updated Feb 5, 2025Feb 5, 2025

    • EF_QSPI_FLASH_WRITER

      Public
      Verilog
      •0•0•0•0•Updated Feb 4, 2025Feb 4, 2025

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •2•14•7•3•Updated Feb 4, 2025Feb 4, 2025

    • sky130_aa_ip__programmable_pll

      Public
      Chipaloza Challange A Low Phase Noise Programmable Differential Clock Generator
      Tcl
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 2, 2025Feb 2, 2025

    • volare

      Public
      Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
      version-managerpdkopenlanepdkspython
      Python
      •
      Apache License 2.0
      •7•63•5•4•Updated Jan 31, 2025Jan 31, 2025

    • EF_USB_CDC_WRAPPER

      Public
      Verilog
      •0•0•0•0•Updated Jan 30, 2025Jan 30, 2025

    • EF_SRAM_1024x32

      Public
      Verilog
      •0•3•6•1•Updated Jan 29, 2025Jan 29, 2025

    • sky130_klayout_pdk

      Public
      Skywaters 130nm Klayout PDK
      pdkskywaterschipdesign
      Python
      •
      Apache License 2.0
      •13•22•9•1•Updated Jan 29, 2025Jan 29, 2025

    • EF_PSRAM_CTRL

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•3•1•Updated Jan 29, 2025Jan 29, 2025