[CPU] Fix modernize-concat-nested-namespaces clang-tidy remarks

src/plugins/intel_cpu/src/.clang-tidy

@@ -31,7 +31,6 @@
 # -readability-implicit-bool-conversion,
 # -readability-magic-numbers, cppcoreguidelines-avoid-magic-numbers
 # -readability-function-cognitive-complexity. Reasonable way to enforce splitting complex code into simple functions
-# -modernize-concat-nested-namespaces. More compact way when C++17 is available
 
 Checks: >
   -*,
@@ -58,7 +57,6 @@ Checks: >
   -cppcoreguidelines-avoid-magic-numbers,
   -readability-uppercase-literal-suffix,
   -readability-function-cognitive-complexity,
-  -modernize-concat-nested-namespaces,
 # Treat warnings as errors
 WarningsAsErrors: '*'
 # Use clang-format for applied fixes

src/plugins/intel_cpu/src/allocation_context.hpp

@@ -8,8 +8,7 @@
 #include <unordered_map>
 #include <vector>
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 class Node;
 class Edge;
@@ -22,5 +21,4 @@ struct AllocationContext {
     std::vector<size_t> syncPoints;
 };
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cache/multi_cache.cpp

@@ -4,10 +4,8 @@
 
 #include "multi_cache.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 std::atomic_size_t MultiCache::_typeIdCounter{0};
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/compiled_model.cpp

@@ -34,8 +34,7 @@
 
 using namespace ov::threading;
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 struct ImmediateSerialExecutor : public ov::threading::ITaskExecutor {
     void run(ov::threading::Task task) override {
@@ -362,5 +361,4 @@ void CompiledModel::release_memory() {
     }
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/config.cpp

@@ -18,8 +18,7 @@
 #include "utils/debug_capabilities.h"
 #include "utils/precision_support.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 using namespace ov::threading;
 using namespace dnnl::impl::cpu::x64;
@@ -509,5 +508,4 @@ void Config::applyRtInfo(const std::shared_ptr<const ov::Model>& model) {
     }
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_map_scheduling.cpp

@@ -9,8 +9,7 @@
 #include "openvino/runtime/system_conf.hpp"
 #include "openvino/runtime/threading/cpu_streams_info.hpp"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 std::vector<std::vector<int>> apply_scheduling_core_type(ov::hint::SchedulingCoreType& input_type,
                                                          const std::vector<std::vector<int>>& proc_type_table) {
@@ -106,5 +105,4 @@ bool get_cpu_pinning(bool& input_value,
     return result_value;
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_map_scheduling.hpp

@@ -15,8 +15,7 @@
 #include "openvino/runtime/properties.hpp"
 #include "openvino/runtime/threading/istreams_executor.hpp"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 /**
  * @brief      Limit available CPU resource in processors type table according to scheduling core type property
@@ -55,5 +54,4 @@ bool get_cpu_pinning(bool& input_value,
                      const std::vector<std::vector<int>>& proc_type_table,
                      const std::vector<std::vector<int>>& streams_info_table);
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_memory.cpp

@@ -18,8 +18,7 @@
 #    include <utility>
 #endif
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 template <>
 DnnlMemoryDescPtr IMemory::getDescWithType<DnnlMemoryDesc, 0, 0>() const {
     return MemoryDescUtils::convertToDnnlMemoryDesc(getDescPtr());
@@ -729,5 +728,4 @@ MemoryPtr split_vertical(const dnnl::engine& eng,
     return ptr;
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_shape.cpp

@@ -6,8 +6,7 @@
 
 #include "utils/general_utils.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 bool Shape::isCompatible(const VectorDims& vecDims) const {
     if (getRank() != vecDims.size()) {
@@ -77,5 +76,4 @@ Shape mergeShapes(const Shape& lhs, const Shape& rhs) {
     return Shape{resultMinDims, resultMaxDims};
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_streams_calculation.cpp

@@ -27,8 +27,7 @@ using namespace ov::threading;
 #define INIT_VAL     -100
 #define TP_CPU_LIMIT 32
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 void sort_table_by_numa_node_id(const int current_numa_node, std::vector<std::vector<int>>& proc_type_table) {
     if (proc_type_table.size() > 1) {
@@ -761,5 +760,4 @@ void get_num_streams(const int streams, const std::shared_ptr<ov::Model>& model,
     }
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_streams_calculation.hpp

@@ -16,8 +16,7 @@
 #include "graph.h"
 #include "openvino/runtime/properties.hpp"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 /**
  * @brief      Generate streams information table according to processors type table.
  * @param[in]  input_streams is the targeted number of streams set by user via ov::num_streams or the default value.
@@ -114,5 +113,4 @@ void get_num_streams(const int streams, const std::shared_ptr<ov::Model>& model,
  */
 void sort_table_by_numa_node_id(const int current_numa_node, std::vector<std::vector<int>>& proc_type_table);
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_tensor.cpp

@@ -10,8 +10,7 @@
 #include "utils/debug_capabilities.h"
 #include "utils/general_utils.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 Tensor::Tensor(MemoryPtr memptr) : m_memptr{std::move(memptr)} {
     OPENVINO_ASSERT(m_memptr != nullptr);
@@ -106,5 +105,4 @@ std::shared_ptr<ITensor> make_tensor(MemoryPtr mem) {
     return std::make_shared<Tensor>(std::move(mem));
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/cpu_types.cpp

@@ -8,8 +8,7 @@
 
 #include "cpu_shape.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 std::string dim2str(Dim dim) {
     return dim == Shape::UNDEFINED_DIM ? "?" : std::to_string(dim);
@@ -530,5 +529,4 @@ std::string algToString(const Algorithm alg) {
     return "Undefined";
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/dnnl_extension_utils.cpp

@@ -16,8 +16,7 @@
 
 using namespace dnnl;
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 uint8_t DnnlExtensionUtils::sizeOfDataType(dnnl::memory::data_type dataType) {
     switch (dataType) {
@@ -295,5 +294,4 @@ std::string DnnlExtensionUtils::computeWeightsStringHash(const std::shared_ptr<c
     return std::to_string(desc_hash) + "_" + std::to_string(reinterpret_cast<uint64_t>(memory->getData()));
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/dnnl_postops_composer.cpp

@@ -19,8 +19,7 @@
 #include "utils/cpu_utils.hpp"
 #include "utils/debug_capabilities.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 DnnlPostOpsComposer::DnnlPostOpsComposer(const PostOps& postOps,
                                          const dnnl::engine& engine,
@@ -802,5 +801,4 @@ DnnlPrimitiveAttrs DnnlPostOpsComposer::compose() {
     return {attr, dnnlArgs, cpuArgs};
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/dnnl_postops_composer_legacy.cpp

@@ -10,8 +10,7 @@
 
 #include "utils/debug_capabilities.h"
 
-namespace ov {
-namespace intel_cpu {
+namespace ov::intel_cpu {
 
 DnnlPostOpsComposerLegacy::DnnlPostOpsComposerLegacy(const dnnl::engine& engine,
                                                      dnnl::primitive_attr& attr,
@@ -268,5 +267,4 @@ void DnnlPostOpsComposerLegacy::appendClip(const std::vector<float>& low, const
     }
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/edge.cpp

@@ -10,8 +10,8 @@
 #include "openvino/util/pp.hpp"
 
 using namespace dnnl;
-namespace ov {
-namespace intel_cpu {
+
+namespace ov::intel_cpu {
 
 Edge::Edge(const NodePtr& parent, const NodePtr& child, int pr_port, int ch_port)
     : parent(parent),
@@ -668,5 +668,4 @@ std::ostream& operator<<(std::ostream& os, const Edge& edge) {
               << ":" << Edge::statusToString(edge.getStatus());
 }
 
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_conversion_emitters.cpp

@@ -9,9 +9,7 @@
 using namespace dnnl::impl::cpu::aarch64;
 using namespace Xbyak_aarch64;
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 // In aarch64, conversion between f16 and i16/u16 can be done with single instruction. The supported
 // conversion precicions are f32, i32, f16, i8 (byte), u8 (byte). If we introduce an intermediate
@@ -274,6 +272,4 @@ void jit_convert_saturation_emitter::emit_isa(const std::vector<size_t>& in_idxs
     jit_convert_process<TReg>(src, dst, input_type, output_type, true);
 }
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_conversion_emitters.hpp

@@ -6,9 +6,7 @@
 
 #include "jit_emitter.hpp"
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 class jit_convert_emitter : public jit_emitter {
 public:
@@ -89,6 +87,4 @@ class jit_convert_saturation_emitter : public jit_convert_emitter {
     void emit_isa(const std::vector<size_t>& in_idxs, const std::vector<size_t>& out_idxs) const;
 };
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_eltwise_emitters.cpp

@@ -11,9 +11,7 @@
 #include "openvino/core/type/element_type.hpp"
 #include "transformations/cpu_opset/common/op/swish_cpu.hpp"
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 using namespace dnnl::impl::utils;
 using namespace dnnl::impl::cpu;
@@ -2905,6 +2903,4 @@ std::set<std::vector<element::Type>> jit_tanh_emitter::get_supported_precisions(
     return {{element::f32}};
 }
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_eltwise_emitters.hpp

@@ -6,9 +6,7 @@
 
 #include "jit_emitter.hpp"
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 class jit_abs_emitter : public jit_emitter {
 public:
@@ -1194,6 +1192,4 @@ class jit_tanh_emitter : public jit_emitter {
     void emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const;
 };
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_emitter.cpp

@@ -12,9 +12,7 @@
 using namespace dnnl::impl::cpu;
 using namespace dnnl::impl;
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 const std::vector<size_t> jit_emitter::store_gpr_regs = {
     // Parameter/result registers
@@ -338,6 +336,4 @@ void jit_emitter::restore_context(const std::vector<size_t>& gpr_regs,
     }
 }
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64

src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_emitter.hpp

@@ -12,9 +12,7 @@
 #include "snippets/generator.hpp"
 #include "snippets/snippets_isa.hpp"
 
-namespace ov {
-namespace intel_cpu {
-namespace aarch64 {
+namespace ov::intel_cpu::aarch64 {
 
 enum emitter_in_out_map {
     vec_to_vec,
@@ -186,6 +184,4 @@ class jit_emitter : public ov::snippets::Emitter {
                          const std::unordered_set<size_t>& ignore_vec_regs = {}) const;
 };
 
-}  // namespace aarch64
-}  // namespace intel_cpu
-}  // namespace ov
+}  // namespace ov::intel_cpu::aarch64