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Fixups: Implement sign extension + Fixes #65
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This looks to fix #53 |
I added a commit the this PR to fix #48 too. |
The core file and the shorter fixes look fine to me. I'm afraid I don't know the code well enough to give a proper review of the ext stuff, but it looks like it does the job. Only thing I'm wondering is if this will put more logic in the alu_result_o path even when FEATURE_EXT is disabled? Please take a look at that, but I'm happy to see these patches merged anway |
Thanks for the review. It's a good point in the extra logic on alu_result_o. I tried to model it like the other optional features which I assumed would be optimized out when disabled. I will check what I can see in the netlist, I might find I need to fix other optional functions as well. |
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I think you shiuld add round brackets for decode_op_ext_o (in mor1kx_decode) expression in the way:
assign decode_op_ext_o = opc_insn == OR1K_OPCODE_ALU && (opc_alu ==
OR1K_ALU_OPC_EXTBH ||
opc_alu == `OR1K_ALU_OPC_EXTW);
Taken from the latest fusesoc-cores
Reported by Alexander that he was seeing XXX's on the flag on init. Adding a reset seems to work.
This has been defined as a feature but never implemented. Tested with or1k-test on iverilog.
Found in or1k-tests `or1k-alignillegalinsn`. When jumping to a bad address like 0xff000000 the instruction bus raises an error. At this point the fetch unit is waiting for the cache fill to be full and never checks for error causing a lockup. This change will allow us to detect an error and stop the cache refill.
This allows us to document it and also control it during builds.
Thank you, I made the change to clean up Also, one strange thing, I am trying to test the mor1kx build with de0_nano-multicore. But Its failing to fit. It seems something has come into mor1kx or another core which is causing us to go over the resource limit now. I am looking into it. Once its fixed I will merge this. Also, I added one more commit to pull the BRANCH PREDICTION parameter up to the mor1kx top. |
Introduced with commit 73bf629 (true_dpram: Use a single sequential block). Change to use 2 clocks to better match what xilinx expects when inferring true dual port RAM. Tested and works on quartus/altera/intel.
I updated the fix for #66 as discussed with Philipp, I am hoping switching to 2 clocks will work for xilinx, it works for altera. |
I am merging this.
Creating issue for multiply carry limitation. |
This all looks good to me. Nice work folks! |
Working on fixing up some of the test cases in or1k-tests. I found l.ext* instructions were never implemented. I implemented it using case because I thought its easy to read like that. But if others have suggestions let me know.