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spr_bus_ack_o reset issue #127
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stffrdhrn
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Jul 9, 2021
Issue: openrisc#127 The reset and error cases override the state to IDLE, we should check invalidate after this to avoid setting the spr_bus_ack_o when we are not going to invalidate. This was detected via formal verification.
I posted a fix for this does it also fix formal? |
OK, it doesn't cater for the case when |
stffrdhrn
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Jul 10, 2021
Issue: openrisc#127 The reset and error cases override the state to IDLE, but if we are invalidating the spr_bus_ack_o stays set which should probably not cause any problem but is showing up as an issue in formal verification. Ensure reset and error override invalidate and also reset the ack output signal on reset.
I pushed another update, how does it look now? |
It passes the test, the issue is resolved. |
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This issue is applicable to the mor1kx_icache module. After resetting, the state moves to IDLE but spr_bus_ack_o can be high if spr strobe/write signals stays high during reset. This is possible as spr stb/we signals are not reset in the ctrl module.
Assertion Failed:
Trace showing issue:
The text was updated successfully, but these errors were encountered: