Add RTL configuration RVZifencei #2745
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Add RTL configuration RVZifencei
I have a doubt about this line in the "commit stage"
I don't know if the RVZifencei configuration should block the continuation of this logic (via fence_i_o).
Is this a special case of the WB reusing the fence_i_o logic or is this linked to the only case of a fence_i instruction?
if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && CVA6Cfg.DCacheType == config_pkg::WB && commit_instr_i[0].fu != STORE)) begin