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Separate the routing for control flows and data flows #1082

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merged 14 commits into from
Feb 12, 2025
Merged

Separate the routing for control flows and data flows #1082

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a677fe5
init commit
Yu-Zhewen Feb 6, 2025
282596d
fix test
Yu-Zhewen Feb 6, 2025
d04e59f
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 6, 2025
49b8357
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 7, 2025
6bdfa15
fix format
Yu-Zhewen Feb 7, 2025
5f0ff48
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 7, 2025
e823736
test different orders
Yu-Zhewen Feb 9, 2025
6d163c6
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 11, 2025
80f28d1
add more comments and cleanup
Yu-Zhewen Feb 11, 2025
7644c29
rename pre-routed to prior/previously-routed
Yu-Zhewen Feb 12, 2025
75dcf00
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 12, 2025
23b93ab
rename test and use explicit types
Yu-Zhewen Feb 12, 2025
13eb2f1
Merge branch 'main' into zhewen_priority_routing
Yu-Zhewen Feb 12, 2025
5acf759
resolve comments
Yu-Zhewen Feb 12, 2025
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3 changes: 2 additions & 1 deletion compiler/plugins/target/AMD-AIE/aie/AIEOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -236,7 +236,8 @@ def AIE_PacketRuleOp: AIE_Op<"rule"> {
let arguments = (
ins I8Attr:$mask,
I8Attr:$value,
Index:$amsel
Index:$amsel,
OptionalAttr<DenseI32ArrayAttr>:$packet_ids
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When lowering packet_flow to packet_rule, the IDs can be used to calculate the mask and value. However, the reverse operation (calculating the IDs from the mask and value) is not feasible, as we will probably get a superset of actual IDs. This can cause issues during the second run of the router.

);
let summary = "Packet switched routing rule";
let assemblyFormat = [{
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450 changes: 306 additions & 144 deletions compiler/plugins/target/AMD-AIE/aie/AMDAIECreatePathFindFlows.cpp
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1 change: 1 addition & 0 deletions compiler/plugins/target/AMD-AIE/aie/PassDetail.h
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Expand Up @@ -13,6 +13,7 @@
namespace mlir::iree_compiler::AMDAIE {

#define GEN_PASS_DECL
#define GEN_PASS_DEF_AMDAIEROUTEFLOWSWITHPATHFINDER
#define GEN_PASS_DEF_AMDAIECORETOSTANDARD

#include "aie/Passes.h.inc"
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9 changes: 2 additions & 7 deletions compiler/plugins/target/AMD-AIE/aie/Passes.h
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Expand Up @@ -13,11 +13,6 @@

namespace mlir::iree_compiler::AMDAIE {

struct AIERoutePathfinderFlowsOptions {
bool clRouteCircuit = true;
bool clRoutePacket = true;
};

std::unique_ptr<OperationPass<xilinx::AIE::DeviceOp>>
createAMDAIEAssignBufferAddressesBasicPass();
std::unique_ptr<OperationPass<xilinx::AIE::DeviceOp>>
Expand All @@ -29,7 +24,8 @@ createAMDAIELocalizeLocksPass();
std::unique_ptr<OperationPass<xilinx::AIE::DeviceOp>>
createAMDAIENormalizeAddressSpacesPass();
std::unique_ptr<OperationPass<xilinx::AIE::DeviceOp>>
createAMDAIEPathfinderPass();
createAMDAIERouteFlowsWithPathfinderPass(
AMDAIERouteFlowsWithPathfinderOptions options = {});
std::unique_ptr<OperationPass<ModuleOp>> createAMDAIECoreToStandardPass(
AMDAIECoreToStandardOptions options = {});
std::unique_ptr<OperationPass<xilinx::AIE::DeviceOp>>
Expand All @@ -39,7 +35,6 @@ void registerAMDAIEAssignBufferAddressesBasic();
void registerAMDAIEAssignBufferDescriptorIDs();
void registerAMDAIELocalizeLocks();
void registerAMDAIENormalizeAddressSpaces();
void registerAMDAIERoutePathfinderFlows();
void registerAMDAIEDmaToNpu();

} // namespace mlir::iree_compiler::AMDAIE
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19 changes: 19 additions & 0 deletions compiler/plugins/target/AMD-AIE/aie/Passes.td
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Expand Up @@ -8,6 +8,25 @@
#define AMDAIE_AIE_PASSES

include "mlir/Pass/PassBase.td"
include "AIEOps.td"

def AMDAIERouteFlowsWithPathfinder :
Pass<"amdaie-create-pathfinder-flows", "xilinx::AIE::DeviceOp"> {
let summary = "Using Dijkstra's pathfinding algorithm to route"
"`aie.flow` and `aie.packet_flow` operations through switchboxes";
let constructor = "mlir::iree_compiler::AMDAIE::createAMDAIERouteFlowsWithPathfinderPass()";
let options = [
Option<"routeCircuit", "route-circuit", "bool", /*default=*/"true",
"Enable `aie.flow` routing.">,
Option<"routePacket", "route-packet", "bool", /*default=*/"true",
"Enable `aie.packet_flow` routing.">,
Option<"routeCtrl", "route-ctrl", "bool", /*default=*/"true",
"Enable routing for control flows, i.e., flows where a `CTRL` port is either the source or the destination.">,
Option<"routeData", "route-data", "bool", /*default=*/"true",
"Enable routing for data flows, i.e., flows where both the source and destination are non-`CTRL` ports.">,
];
}


def AMDAIECoreToStandard :
Pass<"amdaie-standard-lowering", "ModuleOp"> {
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8 changes: 4 additions & 4 deletions compiler/plugins/target/AMD-AIE/aie/test/test_pktflow_weight_pusher.mlir
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Expand Up @@ -210,10 +210,10 @@
// CHECK: aie.rule(24, 0, %[[VAL_69]])
// CHECK: }
// CHECK: aie.packet_rules(EAST : 0) {
// CHECK: aie.rule(31, 9, %3)
// CHECK: aie.rule(31, 10, %3)
// CHECK: aie.rule(27, 11, %3)
// CHECK: aie.rule(24, 8, %2)
// CHECK: aie.rule(31, 13, %[[VAL_70]])
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Due to the changes on
https://github.com/nod-ai/iree-amd-aie/pull/1082/files#diff-b5e43c7f6b1588e5d27b15fcfcc885d11c8d9753b8b1c93448ecf1ba3ee11bbcL849-R947

// CHECK: aie.rule(31, 14, %[[VAL_70]])
// CHECK: aie.rule(27, 8, %[[VAL_70]])
// CHECK: aie.rule(24, 8, %[[VAL_71]])
// CHECK: }
// CHECK: }
// CHECK: %[[TILE_7_5:.*]] = aie.tile(7, 5)
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