Signal with an external name cannot be assigned concurrently

[am9417]

Following structure gives error. I.e. when assigning a signal from an external name inside an architecture (concurrent assignment statement).

** Error: unexpected << while parsing concurrent statement, expecting one of process, postponed, component, entity, configuration, with, assert, block, if, for, case, ( or identifier

architecture arc of ent is
  signal x : std_logic;
begin
  << signal .some.external.name : std_logic >> <= x;
end architecture;

My workaround is to wrap the concurrent assignment into a process:

architecture arc of ent is
  signal x : std_logic;
begin
  process(all)
  begin
    << signal .some.external.name : std_logic >> <= x;
  end process;
end architecture;

and the error disappears and the unit can be analyzed.