iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator

Changes since V1:

Apply Jonathan's review feedback:
Revise device status attribute names, and split documentation into two sections.
Add additional comments, and fix indention issues.
Remove pointless zero initializations.
Revise return value handling.
Simplify some code sections.
Split store_eeprom and sync handling into separate functions.
Use strtobool where applicable.
Document platform data structures using kernel-doc style.

Use dev_to_iio_dev
write_raw IIO_CHAN_INFO_FREQUENCY: Reject values <= 0
Make patch target drivers/iio

Changes since V2:

Use for_each_clear_bit() and __set_bit() where applicable.
Add descriptive comment.
Avoid temporary for struct regulator.
spi_device_id name use ad9523-1, ad9523 will be added later.

Signed-off-by: Michael Hennerich <[email protected]>
Acked-by: Jonathan Cameron <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523

@@ -0,0 +1,37 @@
+What:		/sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
+What:		/sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
+What:		/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
+What:		/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
+What:		/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
+What:		/sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
+KernelVersion:	3.4.0
+Contact:	[email protected]
+Description:
+		Reading returns either '1' or '0'.
+		'1' means that the clock in question is present.
+		'0' means that the clock is missing.
+
+What:		/sys/bus/iio/devices/iio:deviceX/pllY_locked
+KernelVersion:	3.4.0
+Contact:	[email protected]
+Description:
+		Reading returns either '1' or '0'. '1' means that the
+		pllY is locked.
+
+What:		/sys/bus/iio/devices/iio:deviceX/store_eeprom
+KernelVersion:	3.4.0
+Contact:	[email protected]
+Description:
+		Writing '1' stores the current device configuration into
+		on-chip EEPROM. After power-up or chip reset the device will
+		automatically load the saved configuration.
+
+What:		/sys/bus/iio/devices/iio:deviceX/sync_dividers
+KernelVersion:	3.4.0
+Contact:	[email protected]
+Description:
+		Writing '1' triggers the clock distribution synchronization
+		functionality. All dividers are reset and the channels start
+		with their predefined phase offsets (out_altvoltageY_phase).
+		Writing this file has the effect as driving the external
+		/SYNC pin low.

drivers/iio/Kconfig

@@ -51,5 +51,6 @@ config IIO_CONSUMERS_PER_TRIGGER
 source "drivers/iio/adc/Kconfig"
 source "drivers/iio/amplifiers/Kconfig"
 source "drivers/iio/light/Kconfig"
+source "drivers/iio/frequency/Kconfig"
 
 endif # IIO

drivers/iio/Makefile

@@ -12,3 +12,4 @@ obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o
 obj-y += adc/
 obj-y += amplifiers/
 obj-y += light/
+obj-y += frequency/

drivers/iio/frequency/Kconfig

@@ -0,0 +1,23 @@
+#
+# Frequency
+#	Direct Digital Synthesis drivers (DDS)
+#	Clock Distribution device drivers
+#	Phase-Locked Loop (PLL) frequency synthesizers
+#
+
+menu "Frequency Synthesizers DDS/PLL"
+
+menu "Clock Generator/Distribution"
+
+config AD9523
+	tristate "Analog Devices AD9523 Low Jitter Clock Generator"
+	depends on SPI
+	help
+	  Say yes here to build support for Analog Devices AD9523 Low Jitter
+	  Clock Generator. The driver provides direct access via sysfs.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called ad9523.
+
+endmenu
+endmenu

drivers/iio/frequency/Makefile

@@ -0,0 +1,5 @@
+#
+# Makefile iio/frequency
+#
+
+obj-$(CONFIG_AD9523) += ad9523.o