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F7 improvements and attempts at CLR RAM optimisations for some boards (…
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…#370)

* changed F796I to reflect changes in ChibiOS

* Updated F746 to match latest changes in ChibiOS

* attempt at optimising some boards for the CLR #366 - further optimisations probably still possible. Some boards not done (namely quail and F0)

* change heap size of F429
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@networkfusion @josesimoes
networkfusion authored and josesimoes committed Jun 29, 2017
1 parent 9bdea56 commit 5f60606
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Showing 11 changed files with 44 additions and 15 deletions.
2 changes: 1 addition & 1 deletion targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR.ld
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Expand Up @@ -67,7 +67,7 @@ REGION_ALIAS("DATA_RAM_LMA", flash);
REGION_ALIAS("BSS_RAM", ram0);

/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
REGION_ALIAS("HEAP_RAM", ram4);

/* RAM region to be used for the nanoFramework CLR managed heap.*/
REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0);
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2 changes: 1 addition & 1 deletion targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAG
# the size of the CLR managed heap is defined here
###################################################
set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x0")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x9000")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x2B000")


set(NANOBOOTER_HEX_FILE ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.hex)
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10 changes: 6 additions & 4 deletions targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 2
#define STM32_PLLI2SQ_VALUE 2
Expand All @@ -59,9 +59,11 @@
#define STM32_PLLSAIP_VALUE 2
#define STM32_PLLSAIQ_VALUE 2
#define STM32_PLLSAIR_VALUE 2
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_SAI1SEL STM32_SAI1SEL_SAIPLL
#define STM32_SAI2SEL STM32_SAI2SEL_SAIPLL
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
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9 changes: 9 additions & 0 deletions targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,15 @@ SECTIONS
/* Code rules inclusion.*/
INCLUDE rules_code.ld

/*
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// rules_clr.ld have to be included **BEFORE** the rules_data.ld
// this is because the CRT heap (processed in rules_data.ld) takes up all the remaining free space of the memory region where it's assigned
// the size of the managed heap (processed in rules_clr.ld) is set in each target configuration
// in case it shares the same region as the CRT heap it won't have any room left if the CRT heap is assigned first
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*

/* nanoCLR rules inclusion.*/
INCLUDE rules_clr.ld

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5 changes: 3 additions & 2 deletions targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 2
#define STM32_PLLI2SQ_VALUE 2
Expand All @@ -59,7 +59,8 @@
#define STM32_PLLSAIP_VALUE 2
#define STM32_PLLSAIQ_VALUE 2
#define STM32_PLLSAIR_VALUE 2
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_SAIPLL
#define STM32_SAI2SEL STM32_SAI2SEL_SAIPLL
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
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2 changes: 1 addition & 1 deletion targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAG
# the size of the CLR managed heap is defined here
###################################################
set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x0")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x9000")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x2A758")


set(NANOBOOTER_HEX_FILE ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.hex)
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2 changes: 1 addition & 1 deletion targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ REGION_ALIAS("DATA_RAM_LMA", flash);
REGION_ALIAS("BSS_RAM", ram0);

/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
REGION_ALIAS("HEAP_RAM", ram4);

/* RAM region to be used for the nanoFramework CLR managed heap.*/
REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0);
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2 changes: 1 addition & 1 deletion targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAG
# the size of the CLR managed heap is defined here
###################################################
set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x0")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x9000")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__clr_managed_heap_size__=0x4B000")


set(NANOBOOTER_HEX_FILE ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.hex)
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8 changes: 6 additions & 2 deletions targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
Expand All @@ -59,9 +59,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
Expand Down Expand Up @@ -103,8 +105,10 @@
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11

/*
* DAC driver system settings.
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9 changes: 9 additions & 0 deletions targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,15 @@ SECTIONS
/* Code rules inclusion.*/
INCLUDE rules_code.ld

/*
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// rules_clr.ld have to be included **BEFORE** the rules_data.ld
// this is because the CRT heap (processed in rules_data.ld) takes up all the remaining free space of the memory region where it's assigned
// the size of the managed heap (processed in rules_clr.ld) is set in each target configuration
// in case it shares the same region as the CRT heap it won't have any room left if the CRT heap is assigned first
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*

/* nanoCLR rules inclusion.*/
INCLUDE rules_clr.ld

Expand Down
8 changes: 6 additions & 2 deletions targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
Expand All @@ -59,9 +59,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
Expand Down Expand Up @@ -103,8 +105,10 @@
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11

/*
* DAC driver system settings.
Expand Down

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