Rework inline functions

- Move all inline functions from headers to code files. - Add missing declarations to nanoHAL_v2. - Add forced breakpoint in ESP32 in functions requiring it. Signed-off-by: José Simões <[email protected]>
nanoframework · Feb 21, 2019 · 3469c07 · 3469c07
1 parent 125bb68
commit 3469c07
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Showing 7 changed files with 91 additions and 31 deletions.
diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h
@@ -298,6 +298,18 @@ __inline void debug_printf( const char *format, ... ) {}
 #endif
 //--//
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+bool Target_HasNanoBooter();
+void HARD_Breakpoint();
+bool Target_ConfigUpdateRequiresErase();
+
+#ifdef __cplusplus
+}
+#endif
+
 // Watchdog driver
 #include <nanoHAL_Watchdog.h>
 

diff --git a/targets/CMSIS-OS/ChibiOS/Include/targetHAL.h b/targets/CMSIS-OS/ChibiOS/Include/targetHAL.h
@@ -7,8 +7,8 @@
 #define _TARGET_HAL_H_
 
 #include <target_board.h>
-#include <nanoWeak.h>
 #include <cmsis_gcc.h>
+#include <nanoHAL_v2.h>
 
 #define GLOBAL_LOCK(x)              chSysLock();
 #define GLOBAL_UNLOCK(x);           chSysUnlock();
@@ -29,12 +29,6 @@
 
 #if !defined(BUILD_RTM)
 
-inline void HARD_Breakpoint() 
-{
-    __BKPT(0);
-    while(true) { /*nop*/ }
-};
-
 #define HARD_BREAKPOINT()     HARD_Breakpoint()
 
 // #if defined(_DEBUG)
@@ -50,15 +44,8 @@ inline void HARD_Breakpoint()
 
 #endif  // !defined(BUILD_RTM)
 
-inline bool Target_HasNanoBooter() { return true; };
-
 #define NANOCLR_STOP() CPU_Reset();
 
-// Provides information whether the configuration block storage requires erase command before sending the update command
-// The 'weak' implementation for ChibiOS targets is true
-// If a target implements the store differently it has to provide a 'strong' implementation of this.
-__nfweak bool Target_ConfigUpdateRequiresErase() { return true; };
-
 extern int HeapBegin;
 extern int HeapEnd;
 

diff --git a/targets/CMSIS-OS/ChibiOS/common/targetHAL.c b/targets/CMSIS-OS/ChibiOS/common/targetHAL.c
@@ -4,9 +4,33 @@
 //
 
 #include <ch.h>
+#include <nanoWeak.h>
 
 void HAL_AssertEx()
 {
     __BKPT(0);
     while(true) { /*nop*/ }
 }
+
+#if !defined(BUILD_RTM)
+
+void HARD_Breakpoint() 
+{
+    __BKPT(0);
+    while(true) { /*nop*/ }
+};
+
+#endif  // !defined(BUILD_RTM)
+
+// Provides information whether the configuration block storage requires erase command before sending the update command
+// The 'weak' implementation for ChibiOS targets is true
+// If a target implements the store differently it has to provide a 'strong' implementation of this.
+__nfweak bool Target_ConfigUpdateRequiresErase()
+{
+    return true;
+};
+
+bool Target_HasNanoBooter()
+{ 
+    return false; 
+};
diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Power.c b/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Power.c
@@ -13,12 +13,23 @@
 
 uint32_t WakeupReasonStore;
 
-inline void CPU_Reset(){ NVIC_SystemReset(); };
+inline void CPU_Reset()
+{ 
+    NVIC_SystemReset(); 
+};
 
-inline bool CPU_IsSoftRebootSupported() { return true; };
+inline bool CPU_IsSoftRebootSupported()
+{ 
+    return true; 
+};
 
 // CPU sleep is not currently implemented in this target
-inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents) { (void)level; (void)wakeEvents;  };
+inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents)
+{ 
+    (void)level;
+    (void)wakeEvents;
+
+};
 
 void CPU_SetPowerMode(PowerLevel_type powerLevel)
 {

diff --git a/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h b/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h
@@ -7,7 +7,6 @@
 #define _TARGET_HAL_H_
 
 #include <target_board.h>
-#include <nanoWeak.h>
 #include <esp32_os.h>
 
 extern portMUX_TYPE globalLockMutex;
@@ -37,8 +36,6 @@ extern portMUX_TYPE globalLockMutex;
 
 #if !defined(BUILD_RTM)
 
-inline void HARD_Breakpoint() { };
-
 #define HARD_BREAKPOINT()     HARD_Breakpoint()
 
 // #if defined(_DEBUG)
@@ -54,14 +51,8 @@ inline void HARD_Breakpoint() { };
 
 #endif  // !defined(BUILD_RTM)
 
-inline bool Target_HasNanoBooter() { return false; };
-
 #define NANOCLR_STOP() HARD_BREAKPOINT()
 
-// Provides information whether the configuration block storage requires erase command before sending the update command
-// ESP32 is storing this using its non-volatile storage therefore no erase is required.
-__nfweak bool Target_ConfigUpdateRequiresErase() { return false; };
-
 extern int HeapBegin;
 extern int HeapEnd;
 

diff --git a/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL.c b/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL.c
@@ -4,9 +4,33 @@
 //
 
 #include <esp32_os.h>
+#include <nanoWeak.h>
+#include <nanoHAL_v2.h>
 
-void HAL_AssertEx()
+inline void HAL_AssertEx()
 {
-    //__BKPT(0);
+    asm("break.n 1");
     while(true) { /*nop*/ }
 }
+
+#if !defined(BUILD_RTM)
+
+inline void HARD_Breakpoint() 
+{
+    asm("break.n 1");
+    while(true) { /*nop*/ }
+};
+
+#endif  // !defined(BUILD_RTM)
+
+// Provides information whether the configuration block storage requires erase command before sending the update command
+// ESP32 is storing this using its non-volatile storage therefore no erase is required.
+__nfweak bool Target_ConfigUpdateRequiresErase()
+{ 
+    return false;
+};
+
+inline bool Target_HasNanoBooter()
+{ 
+    return false; 
+};
diff --git a/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Power.c b/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Power.c
@@ -6,12 +6,23 @@
 #include <esp32_os.h>
 #include <nanoHAL_v2.h>
 
-inline void CPU_Reset(){ esp_restart(); };
+inline void CPU_Reset()
+{ 
+    esp_restart(); 
+};
 
 // CPU sleep is not currently implemented in this target
-inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents){ (void)level; (void)wakeEvents; };
+inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents)
+{ 
+    (void)level;
+    (void)wakeEvents;
 
-inline bool CPU_IsSoftRebootSupported() { return true; };
+};
+
+inline bool CPU_IsSoftRebootSupported()
+{ 
+    return true;
+};
 
 void CPU_SetPowerMode(PowerLevel_type powerLevel)
 {