correct handling of T bit changes w/o pipeline flush on arm9

melonDS-emu · Nov 8, 2024 · 60a819c · 60a819c
1 parent 5091061
commit 60a819c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/ARMInterpreter.cpp b/src/ARMInterpreter.cpp
@@ -129,7 +129,7 @@ void A_MSR_IMM(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");
@@ -199,7 +199,7 @@ void A_MSR_REG(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");