Computer Architecture & Design
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This project involves the creation of a RISC (Reduced Instruction Set Computer) CPU modeled after the MIPS processor architecture, which is capable of executing a set of 20 instructions.
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The design incorporates the PC unit, next-address unit, register file (regfile), ALU, instruction cache (icache), data cache (dcache), sign-extend and two multiplexers components.
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Various synthesizable VHDL styles, including structural designs utilizing port maps, processes, and Carry Save Adder (CSA) statements, were employed in the development of the processor.
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These designs underwent verification through Modelsim simulations and were subsequently implemented on the Xilinx Nexys A7 FPGA board.
