Work on the FIFO byte ptr

mbtaylor1982 · Apr 19, 2024 · c61e332 · c61e332
1 parent 73a14f6
commit c61e332
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Showing 4 changed files with 31 additions and 19 deletions.
diff --git a/RTL/FIFO/fifo_byte_ptr.v b/RTL/FIFO/fifo_byte_ptr.v
@@ -22,18 +22,21 @@
 module fifo_byte_ptr(
     input CLK,
     input INCBO,
-    input MID25,
+    input MID25, //MID25 is used to set the MSB of the BytePtr depending on if it is a transfer to odd or even address
     input ACR_WR,
     input H_0C,
     input RST_FIFO_,
 
-    output reg [1:0] PTR
+    output [1:0] PTR
 );
 
+
 wire A;
 wire Z;
 reg B;
 reg S;
+reg BO0;
+reg BO1;
 
     MUX2 u_MUX2 (
         .A  (A),  // input A,
@@ -42,10 +45,11 @@ reg S;
         .Z  (Z)   // output,
     );
 
-assign A = ~(PTR[0] ^ PTR[1]);
+assign A = ~(BO1 ^ BO0);
+assign PTR = {BO1, BO0};
 
 //added to eliminate glitches in the signals B and S.
-always @(negedge CLK or negedge RST_FIFO_) begin
+always @(posedge CLK or negedge RST_FIFO_) begin
     if (~RST_FIFO_) begin
         B <= 1'b0;
         S <= 1'b0;
@@ -58,14 +62,16 @@ end
 
 always @(posedge CLK or negedge RST_FIFO_) begin
     if (~RST_FIFO_) begin
-        PTR <= 2'b11;
+        BO0 <= 1'b0;
+        BO1 <= 1'b0;
     end
     else begin
         if (INCBO) begin
-            PTR <= {Z, ~PTR[0]};
+            BO0 <= ~BO0;
+            BO1 <= Z;
         end
         if (ACR_WR)
-            PTR <= {Z, PTR[0]};
+            BO1 <= Z;
     end
 end
 

diff --git a/RTL/FIFO/fifo_write_strobes.v b/RTL/FIFO/fifo_write_strobes.v
@@ -17,7 +17,7 @@
 // along with dogtag.  If not, see <http://www.gnu.org/licenses/>.
  */
 module fifo_write_strobes(
-    input [1:0] PTR,    
+    input [1:0] PTR,
     input LHWORD,
     input LLWORD,
     input LBYTE_,
@@ -35,6 +35,6 @@ assign BO1 = PTR[1];
 assign UUWS = (!BO1 & !BO0 & !LBYTE_) | LHWORD; // B0
 assign UMWS = (!BO1 & BO0  & !LBYTE_) | LHWORD; // B1
 assign LMWS = (BO1  & !BO0 & !LBYTE_) | LLWORD; // B2
-assign LLWS = (BO0  & BO1  & !LBYTE_) | LLWORD; // B3
+assign LLWS = (BO1  & BO0  & !LBYTE_) | LLWORD; // B3
 
 endmodule
diff --git a/RTL/cocotb/cocotb_fifo.py b/RTL/cocotb/cocotb_fifo.py
@@ -56,13 +56,13 @@ async def fifo_test(dut):
 
     assert dut.WRITE_PTR.value == 0 ,"WRITE_PTR != 0  after reset"
     assert dut.READ_PTR.value == 0 ,"READ_PTR != 0  after reset"
-    assert dut.BYTE_PTR.value == 3 ,"BYTE_PTR != 3  after reset"
+    assert dut.BYTE_PTR.value == 0 ,"BYTE_PTR != 0  after reset"
     assert dut.FIFOEMPTY.value == 1 ,"FIFOEMPTY != 1  after reset"
     assert dut.FIFOFULL.value == 0 ,"FIFOFULL != 0  after reset"
-    assert dut.BO0.value == 1 ,"BO0 != 1  after reset"
-    assert dut.BO1.value == 1 ,"BO1 != 1  after reset"
-    assert dut.BOEQ0.value == 0 ,"BOEQ0 != 0  after reset"
-    assert dut.BOEQ3.value == 1 ,"BOEQ3 != 1  after reset"
+    assert dut.BO0.value == 0 ,"BO0 != 0  after reset"
+    assert dut.BO1.value == 0 ,"BO1 != 0  after reset"
+    assert dut.BOEQ0.value == 1 ,"BOEQ0 != 1  after reset"
+    assert dut.BOEQ3.value == 0 ,"BOEQ3 != 0  after reset"
 
     await ClockCycles(dut.CLK, 2, True)    
 
@@ -80,7 +80,8 @@ async def fifo_test(dut):
             dut.INCBO.value = 1
             await ClockCycles(dut.CLK, 1, True) 
             dut.INCBO.value = 0
-        assert dut.BOEQ3.value == 1 ,"BOEQ3 != 1  after long word transfered"        
+        assert dut.BOEQ3.value == 0 ,"BOEQ3 != 0  after long word transfered"
+        assert dut._id("BUFFER[%d]" % dut.WRITE_PTR.value, extended=False).value == dut.FIFO_ID.value , "value %#x was not transferd to FIFO buffer" %dut.FIFO_ID.value
         await ClockCycles(dut.CLK, 1, True) 
         dut.INCNI.value = 1
         dut.INCFIFO.value = 1

diff --git a/RTL/cocotb/cocotb_resdmac.py b/RTL/cocotb/cocotb_resdmac.py
@@ -178,24 +178,29 @@ async def RESDMAC_test(dut):
     #7 Test DMA READ (from scsi to memory) cycle
     await reset_dut(dut._id("_RST", extended=False), 40)
 
+
+
     #Setup DMA Direction to Read from SCSI write to Memory
     await write_data(dut, CONTR_REG_ADR, (CONTR_DMA_READ | CONTR_INTENA))
     #start DMA
     await read_data(dut, ST_DMA_STROBE_ADR)
+
     #Set Destination address
-    await write_data(dut, RAMSEY_ACR_REG_ADR, 0x00000008)
-
+    await write_data(dut, RAMSEY_ACR_REG_ADR, 0x00000000)
+   
     dut.PDATA_I.value = 0x0001
 
     #load fifo from scsci
-    while (dut.FIFOFULL == 0):
+    m = 32
+    for j in range (0, m):
+    #while (dut.FIFOFULL == 0):
         dut._id("_DREQ", extended=False).value = 0
         await FallingEdge(dut._id("_DACK", extended=False))
         await FallingEdge(dut._id("_IOR", extended=False))
         dut._id("_DREQ", extended=False).value = 1
         await RisingEdge(dut._id("_DACK", extended=False))
         await ClockCycles(dut.SCLK, 2, True)
-        dut.PDATA_I.value += 0x0001
+        dut.PDATA_I.value = dut.PDATA_I.value + 0x1
 
     #grant bus to SDMAC    
     await RisingEdge(dut._id("BR", extended=False))