This is a simple project to generate generic 'driver' files for use with Verilator.

It is based on the work ferris did for xenowing.

Current limitations -

• Port sizes > 64 bits aren't supported
• Any expressions in the port definition (ie. output [Width - 1:0] data)
• Only generates generic drivers (ie. not like this alu from xenowing)

Todo -

• Command line interface
• Add different output directories for each file type
• Automatically extract 'module port' definition from SystemVerilog file
• Parse 'module port' definitions
• Output a generic driver in CPP
• Output a generic driver in Rust

Stretch Goals -

• Add an option to create a new cargo lib including the the Rust driver file
• Allow custom enum based ports somehow
• Tuples everywhere are very cryptic. Fix this!

Good job, nearly done!

Bugs -

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• Should warn before overwrite? Maybe make a .bak file?
• Rust struct names should be capitalized
• wrong class name!
• bit size in cpp gen.
• bit size in rust gen.

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This is public domain.

For more Verilog & Rust see rust-verilog which this project is partially based on (I also use lalrpop, but I only parse a small portion of SystemVerilog)