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[RISCV] Improve RISCVOperand Printing #126179

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merged 1 commit into from
Feb 7, 2025
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@lenary lenary commented Feb 7, 2025

We've gradually added more information to the RISCVOperand structure, but the debug output has never caught up, which is quite confusing. This adds printing for many of additional the fields in the structure, where they are relevant.

In addition to this, we now have quite a lot of internal registers which share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the same name - so also print the enum value to differentiate these.

We've gradually added more information to the RISCVOperand structure,
but the debug output has never caught up, which is quite confusing. This
adds printing for many of additional the fields in the structure, where
they are relevant.

In addition to this, we now have quite a lot of internal registers which
share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the
same name - so also print the enum value to differentiate these.
@llvmbot
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llvmbot commented Feb 7, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

We've gradually added more information to the RISCVOperand structure, but the debug output has never caught up, which is quite confusing. This adds printing for many of additional the fields in the structure, where they are relevant.

In addition to this, we now have quite a lot of internal registers which share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the same name - so also print the enum value to differentiate these.


Full diff: https://github.com/llvm/llvm-project/pull/126179.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+6-3)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c51c4201ebd18ca..069c77810c9d674 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1116,18 +1116,21 @@ struct RISCVOperand final : public MCParsedAsmOperand {
 
     switch (Kind) {
     case KindTy::Immediate:
-      OS << *getImm();
+      OS << "<imm: " << *Imm.Val << " " << (Imm.IsRV64 ? "rv64" : "rv32")
+         << ">";
       break;
     case KindTy::FPImmediate:
+      OS << "<fpimm: " << FPImm.Val << ">";
       break;
     case KindTy::Register:
-      OS << "<register " << RegName(getReg()) << ">";
+      OS << "<reg: " << RegName(Reg.RegNum) << " (" << Reg.RegNum
+         << (Reg.IsGPRAsFPR ? ") GPRasFPR>" : ")>");
       break;
     case KindTy::Token:
       OS << "'" << getToken() << "'";
       break;
     case KindTy::SystemRegister:
-      OS << "<sysreg: " << getSysReg() << '>';
+      OS << "<sysreg: " << getSysReg() << " (" << SysReg.Encoding << ")>";
       break;
     case KindTy::VType:
       OS << "<vtype: ";

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LGTM

@lenary lenary merged commit 5566bfa into llvm:main Feb 7, 2025
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@lenary lenary deleted the pr/asm-parser-debug branch February 7, 2025 18:58
Icohedron pushed a commit to Icohedron/llvm-project that referenced this pull request Feb 11, 2025
We've gradually added more information to the RISCVOperand structure,
but the debug output has never caught up, which is quite confusing. This
adds printing for many of additional the fields in the structure, where
they are relevant.

In addition to this, we now have quite a lot of internal registers which
share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the
same name - so also print the enum value to differentiate these.
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3 participants