[CIR][FrontendAction] Use ClangIR pipeline to emit LLVM bitcode #782
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seven-mile
commented
Aug 9, 2024
| @@ -2,6 +2,9 @@ | |||
| // RUN: FileCheck --input-file=%t.mlir %s -check-prefix=MLIR | |||
| // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll | |||
| // RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM | |||
| // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm-bc %s -o %t.bc | |||
| // RUN: llvm-dis %t.bc -o %t.bc.ll | |||
| // RUN: FileCheck --input-file=%t.bc.ll %s -check-prefix=LLVM | |||
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Intentionally use the same check prefix to ensure that bitcode is equally exercised by check lines.
| @@ -364,6 +356,8 @@ getOutputStream(CompilerInstance &ci, StringRef inFile, | |||
| return ci.createDefaultOutputFile(false, inFile, "mlir"); | |||
| case CIRGenAction::OutputType::EmitLLVM: | |||
| return ci.createDefaultOutputFile(false, inFile, "llvm"); | |||
| case CIRGenAction::OutputType::EmitBC: | |||
| return ci.createDefaultOutputFile(true, inFile, "bc"); | |||
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/*binary=*/true, similar to EmitObj.
Comment on lines
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| case CIRGenAction::OutputType::EmitLLVM: | ||
| case CIRGenAction::OutputType::EmitBC: | ||
| case CIRGenAction::OutputType::EmitObj: | ||
| case CIRGenAction::OutputType::EmitAssembly: { |
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3+1 dup cases are merged.
bcardosolopes
approved these changes
Aug 9, 2024
Hugobros3
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Oct 2, 2024
…#782) This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR. Some refactors about switch cases are also included to avoid too many dups.
smeenai
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to smeenai/clangir
that referenced
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Oct 9, 2024
…#782) This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR. Some refactors about switch cases are also included to avoid too many dups.
smeenai
pushed a commit
to smeenai/clangir
that referenced
this pull request
Oct 9, 2024
…#782) This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR. Some refactors about switch cases are also included to avoid too many dups.
keryell
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Oct 19, 2024
…#782) This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR. Some refactors about switch cases are also included to avoid too many dups.
lanza
pushed a commit
that referenced
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Nov 5, 2024
This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR. Some refactors about switch cases are also included to avoid too many dups.
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This PR enables ClangIR pipeline for LLVM bitcode output when it's specified properly, aligned with the behavior of text-form LLVM IR.
Some refactors about switch cases are also included to avoid too many dups.