Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[CIR][CIRGen][Builtin][Neon] Lower vgetq_lane_bf16, vduph f16 and fb16 #1372

Merged
merged 1 commit into from
Feb 19, 2025
Merged

[CIR][CIRGen][Builtin][Neon] Lower vgetq_lane_bf16, vduph f16 and fb16 #1372

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3895,7 +3895,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vgetq_lane_bf16:
case NEON::BI__builtin_neon_vduph_laneq_bf16:
case NEON::BI__builtin_neon_vduph_laneq_f16: {
llvm_unreachable("NEON::BI__builtin_neon_vduph_laneq_f16 NYI");
return builder.create<cir::VecExtractOp>(getLoc(E->getExprLoc()), Ops[0],
emitScalarExpr(E->getArg(1)));
}
case NEON::BI__builtin_neon_vcvt_bf16_f32:
case NEON::BI__builtin_neon_vcvtq_low_bf16_f32:
Expand Down
20 changes: 12 additions & 8 deletions clang/test/CIR/CodeGen/AArch64/bf16-getset-intrinsics.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -140,14 +140,18 @@ bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
// LLVM: ret bfloat [[VGET_LANE]]
}

// CHECK-LABEL: @test_vgetq_lane_bf16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
// CHECK-NEXT: ret bfloat [[VGETQ_LANE]]
//
// bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
// return vgetq_lane_bf16(v, 7);
// }
bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
return vgetq_lane_bf16(v, 7);

// CIR-LABEL: vgetq_lane_bf16
// CIR: [[TMP0:%.*]] = cir.const #cir.int<7> : !s32i
// CIR: [[TMP1:%.*]] = cir.vec.extract {{.*}}[{{.*}} : !s32i] : !cir.vector<!cir.bf16 x 8>

// LLVM-LABEL: test_vgetq_lane_bf16
// LLVM-SAME: (<8 x bfloat> [[VEC:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[VEC]], i32 7
// LLVM: ret bfloat [[VGET_LANE]]
}

// CHECK-LABEL: @test_vset_lane_bf16(
// CHECK-NEXT: entry:
Expand Down
21 changes: 12 additions & 9 deletions clang/test/CIR/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -471,15 +471,18 @@
// return vtrn2q_f16(a, b);
// }

// CHECK-LABEL: define {{[^@]+}}@test_vduph_laneq_f16
// CHECK-SAME: (<8 x half> noundef [[VEC:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x half> [[VEC]], i32 7
// CHECK-NEXT: ret half [[VGETQ_LANE]]
//
// float16_t test_vduph_laneq_f16(float16x8_t vec) {
// return vduph_laneq_f16(vec, 7);
// }
float16_t test_vduph_laneq_f16(float16x8_t vec) {
return vduph_laneq_f16(vec, 7);

// CIR-LABEL: vduph_laneq_f16
// CIR: [[TMP0:%.*]] = cir.const #cir.int<7> : !s32i
// CIR: [[TMP1:%.*]] = cir.vec.extract {{.*}}[{{.*}} : !s32i] : !cir.vector<!cir.f16 x 8>

// LLVM-LABEL: test_vduph_laneq_f16
// LLVM-SAME: (<8 x half> [[VEC:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x half> [[VEC]], i32 7
// LLVM: ret half [[VGET_LANE]]
}

float16_t test_vduph_lane_f16(float16x4_t vec) {
return vduph_lane_f16(vec, 3);
Expand Down
Loading