[CIR][CIRGen][Dialect] Emit OpenCL Kernel Metadata

clang/include/clang/CIR/Dialect/IR/CIRAttrs.td

@@ -979,4 +979,6 @@ def BitfieldInfoAttr : CIR_Attr<"BitfieldInfo", "bitfield_info"> {
   ];
 }
 
+include "clang/CIR/Dialect/IR/CIROpenCLAttrs.td"
+
 #endif // MLIR_CIR_DIALECT_CIR_ATTRS

clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td

@@ -0,0 +1,95 @@
+//===- CIRAttrs.td - CIR dialect attrs for OpenCL ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the CIR dialect attributes for OpenCL.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_CIR_DIALECT_CIR_OPENCL_ATTRS
+#define MLIR_CIR_DIALECT_CIR_OPENCL_ATTRS
+
+//===----------------------------------------------------------------------===//
+// OpenCLKernelMetadataAttr
+//===----------------------------------------------------------------------===//
+
+def OpenCLKernelMetadataAttr
+    : CIR_Attr<"OpenCLKernelMetadata", "cl.kernel_metadata"> {
+
+  let summary = "OpenCL kernel metadata";
+  let description = [{
+    Provide the required information of an OpenCL kernel for the SPIR-V backend.
+
+    The `work_group_size_hint` and `reqd_work_group_size` parameter are integer
+    arrays with 3 elements that provide hints for the work-group size and the
+    required work-group size, respectively.
+
+    The `vec_type_hint` parameter is a type attribute that provides a hint for
+    the vectorization. It can be a CIR or LLVM type, depending on the lowering
+    stage.
+
+    The `vec_type_hint_signedness` parameter is a boolean that indicates the
+    signedness of the vector type hint. It's useful when LLVM type is set in
+    `vec_type_hint`, which is signless by design. It should be set if and only
+    if the `vec_type_hint` is present.
+
+    The `intel_reqd_sub_group_size` parameter is an integer that restricts the
+    sub-group size to the specified value.
+
+    Example:
+    ```
+    #fn_attr = #cir<extra({cl.kernel_metadata = #cir.cl.kernel_metadata<
+      work_group_size_hint = [8 : i32, 16 : i32, 32 : i32],
+      reqd_work_group_size = [1 : i32, 2 : i32, 4 : i32],
+      vec_type_hint = !s32i,
+      vec_type_hint_signedness = 1,
+      intel_reqd_sub_group_size = 8 : i32
+    >})>
+
+    cir.func @kernel(%arg0: !s32i) extra(#fn_attr) {
+      cir.return
+    }
+    ```
+  }];
+
+  let parameters = (ins
+    OptionalParameter<"ArrayAttr">:$work_group_size_hint,
+    OptionalParameter<"ArrayAttr">:$reqd_work_group_size,
+    OptionalParameter<"TypeAttr">:$vec_type_hint,
+    OptionalParameter<"std::optional<bool>">:$vec_type_hint_signedness,
+    OptionalParameter<"IntegerAttr">:$intel_reqd_sub_group_size
+  );
+
+  let assemblyFormat = "`<` struct(params) `>`";
+
+  let genVerifyDecl = 1;
+
+  let extraClassDeclaration = [{
+    /// Extract the signedness from int or int vector types.
+    static std::optional<bool> isSignedHint(mlir::Type vecTypeHint);
+  }];
+
+  let extraClassDefinition = [{
+    std::optional<bool> $cppClass::isSignedHint(mlir::Type hintQTy) {
+      // Only types in CIR carry signedness
+      if (!mlir::isa<mlir::cir::CIRDialect>(hintQTy.getDialect()))
+        return std::nullopt;
+
+      // See also clang::CodeGen::CodeGenFunction::EmitKernelMetadata
+      auto hintEltQTy = mlir::dyn_cast<mlir::cir::VectorType>(hintQTy);
+      auto isCIRSignedIntType = [](mlir::Type t) {
+        return mlir::isa<mlir::cir::IntType>(t) &&
+               mlir::cast<mlir::cir::IntType>(t).isSigned();
+      };
+      return isCIRSignedIntType(hintQTy) ||
+              (hintEltQTy && isCIRSignedIntType(hintEltQTy.getEltType()));
+    }
+  }];
+
+}
+
+#endif // MLIR_CIR_DIALECT_CIR_OPENCL_ATTRS

clang/include/clang/CIR/MissingFeatures.h

@@ -142,6 +142,7 @@ struct MissingFeatures {
   static bool getFPFeaturesInEffect() { return false; }
   static bool cxxABI() { return false; }
   static bool openCL() { return false; }
+  static bool openCLGenKernelMetadata() { return false; }
   static bool CUDA() { return false; }
   static bool openMP() { return false; }
   static bool openMPRuntime() { return false; }

clang/lib/CIR/CodeGen/CIRGenFunction.cpp

@@ -993,8 +993,7 @@ void CIRGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
     llvm_unreachable("NYI");
 
   if (FD && getLangOpts().OpenCL) {
-    // TODO(cir): Emit OpenCL kernel metadata
-    assert(!MissingFeatures::openCL());
+    buildKernelMetadata(FD, Fn);
   }
 
   // If we are checking function types, emit a function type signature as
@@ -1720,3 +1719,67 @@ CIRGenFunction::buildArrayLength(const clang::ArrayType *origArrayType,
 
   return numElements;
 }
+
+void CIRGenFunction::buildKernelMetadata(const FunctionDecl *FD,
+                                         mlir::cir::FuncOp Fn) {
+  if (!FD->hasAttr<OpenCLKernelAttr>() && !FD->hasAttr<CUDAGlobalAttr>())
+    return;
+
+  // TODO(cir): CGM.genKernelArgMetadata(Fn, FD, this);
+  assert(!MissingFeatures::openCLGenKernelMetadata());
+
+  if (!getLangOpts().OpenCL)
+    return;
+
+  using mlir::cir::OpenCLKernelMetadataAttr;
+
+  mlir::ArrayAttr workGroupSizeHintAttr, reqdWorkGroupSizeAttr;
+  mlir::TypeAttr vecTypeHintAttr;
+  std::optional<bool> vecTypeHintSignedness;
+  mlir::IntegerAttr intelReqdSubGroupSizeAttr;
+
+  if (const VecTypeHintAttr *A = FD->getAttr<VecTypeHintAttr>()) {
+    mlir::Type typeHintValue = getTypes().ConvertType(A->getTypeHint());
+    vecTypeHintAttr = mlir::TypeAttr::get(typeHintValue);
+    vecTypeHintSignedness =
+        OpenCLKernelMetadataAttr::isSignedHint(typeHintValue);
+  }
+
+  if (const WorkGroupSizeHintAttr *A = FD->getAttr<WorkGroupSizeHintAttr>()) {
+    workGroupSizeHintAttr = builder.getI32ArrayAttr({
+        static_cast<int32_t>(A->getXDim()),
+        static_cast<int32_t>(A->getYDim()),
+        static_cast<int32_t>(A->getZDim()),
+    });
+  }
+
+  if (const ReqdWorkGroupSizeAttr *A = FD->getAttr<ReqdWorkGroupSizeAttr>()) {
+    reqdWorkGroupSizeAttr = builder.getI32ArrayAttr({
+        static_cast<int32_t>(A->getXDim()),
+        static_cast<int32_t>(A->getYDim()),
+        static_cast<int32_t>(A->getZDim()),
+    });
+  }
+
+  if (const OpenCLIntelReqdSubGroupSizeAttr *A =
+          FD->getAttr<OpenCLIntelReqdSubGroupSizeAttr>()) {
+    intelReqdSubGroupSizeAttr = builder.getI32IntegerAttr(A->getSubGroupSize());
+  }
+
+  // Skip the metadata attr if no hints are present.
+  if (!vecTypeHintAttr && !workGroupSizeHintAttr && !reqdWorkGroupSizeAttr &&
+      !intelReqdSubGroupSizeAttr)
+    return;
+
+  // Append the kernel metadata to the extra attributes dictionary.
+  mlir::NamedAttrList attrs;
+  attrs.append(Fn.getExtraAttrs().getElements());
+
+  auto kernelMetadataAttr = OpenCLKernelMetadataAttr::get(
+      builder.getContext(), workGroupSizeHintAttr, reqdWorkGroupSizeAttr,
+      vecTypeHintAttr, vecTypeHintSignedness, intelReqdSubGroupSizeAttr);
+  attrs.append(kernelMetadataAttr.getMnemonic(), kernelMetadataAttr);
+
+  Fn.setExtraAttrsAttr(mlir::cir::ExtraFuncAttributesAttr::get(
+      builder.getContext(), attrs.getDictionary(builder.getContext())));
+}

clang/lib/CIR/CodeGen/CIRGenFunction.h

@@ -100,6 +100,10 @@ class CIRGenFunction : public CIRGenTypeCache {
   // enter/leave scopes.
   llvm::DenseMap<const Expr *, mlir::Value> VLASizeMap;
 
+  /// Add OpenCL kernel arg metadata and the kernel attribute metadata to
+  /// the function metadata.
+  void buildKernelMetadata(const FunctionDecl *FD, mlir::cir::FuncOp Fn);
+
 public:
   /// A non-RAII class containing all the information about a bound
   /// opaque value.  OpaqueValueMapping, below, is a RAII wrapper for

clang/lib/CIR/Dialect/IR/CIRAttrs.cpp

@@ -15,6 +15,7 @@
 #include "clang/CIR/Dialect/IR/CIROpsEnums.h"
 #include "clang/CIR/Dialect/IR/CIRTypes.h"
 
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/BuiltinAttributeInterfaces.h"
@@ -498,6 +499,63 @@ LogicalResult DynamicCastInfoAttr::verify(
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// OpenCLKernelMetadataAttr definitions
+//===----------------------------------------------------------------------===//
+
+LogicalResult OpenCLKernelMetadataAttr::verify(
+    ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError,
+    ArrayAttr workGroupSizeHint, ArrayAttr reqdWorkGroupSize,
+    TypeAttr vecTypeHint, std::optional<bool> vecTypeHintSignedness,
+    IntegerAttr intelReqdSubGroupSize) {
+  // If no field is present, the attribute is considered invalid.
+  if (!workGroupSizeHint && !reqdWorkGroupSize && !vecTypeHint &&
+      !vecTypeHintSignedness && !intelReqdSubGroupSize) {
+    emitError() << "metadata attribute without any field present is invalid";
+    return failure();
+  }
+
+  // Check for 3-dim integer tuples
+  auto is3dimIntTuple = [](ArrayAttr arr) {
+    auto isInt = [](Attribute dim) { return mlir::isa<IntegerAttr>(dim); };
+    return arr.size() == 3 && llvm::all_of(arr, isInt);
+  };
+  if (workGroupSizeHint && !is3dimIntTuple(workGroupSizeHint)) {
+    emitError() << "work_group_size_hint must have exactly 3 integer elements";
+    return failure();
+  }
+  if (reqdWorkGroupSize && !is3dimIntTuple(reqdWorkGroupSize)) {
+    emitError() << "reqd_work_group_size must have exactly 3 integer elements";
+    return failure();
+  }
+
+  // Check for co-presence of vecTypeHintSignedness
+  if (!!vecTypeHint != vecTypeHintSignedness.has_value()) {
+    emitError() << "vec_type_hint_signedness should be present if and only if "
+                   "vec_type_hint is set";
+    return failure();
+  }
+
+  if (vecTypeHint) {
+    Type vecTypeHintValue = vecTypeHint.getValue();
+    if (mlir::isa<cir::CIRDialect>(vecTypeHintValue.getDialect())) {
+      // Check for signedness alignment in CIR
+      if (isSignedHint(vecTypeHintValue) != vecTypeHintSignedness) {
+        emitError() << "vec_type_hint_signedness must match the signedness of "
+                       "the vec_type_hint type";
+        return failure();
+      }
+      // Check for the dialect of type hint
+    } else if (!LLVM::isCompatibleType(vecTypeHintValue)) {
+      emitError() << "vec_type_hint must be a type from the CIR or LLVM "
+                     "dialect";
+      return failure();
+    }
+  }
+
+  return success();
+}
+
 //===----------------------------------------------------------------------===//
 // CIR Dialect
 //===----------------------------------------------------------------------===//

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -1523,12 +1523,13 @@ class CIRFuncLowering : public mlir::OpConversionPattern<mlir::cir::FuncOp> {
   /// to the name of the attribute in ODS.
   static StringRef getLinkageAttrNameString() { return "linkage"; }
 
+  /// Convert the `cir.func` attributes to `llvm.func` attributes.
   /// Only retain those attributes that are not constructed by
   /// `LLVMFuncOp::build`. If `filterArgAttrs` is set, also filter out
   /// argument attributes.
   void
-  filterFuncAttributes(mlir::cir::FuncOp func, bool filterArgAndResAttrs,
-                       SmallVectorImpl<mlir::NamedAttribute> &result) const {
+  lowerFuncAttributes(mlir::cir::FuncOp func, bool filterArgAndResAttrs,
+                      SmallVectorImpl<mlir::NamedAttribute> &result) const {
     for (auto attr : func->getAttrs()) {
       if (attr.getName() == mlir::SymbolTable::getSymbolAttrName() ||
           attr.getName() == func.getFunctionTypeAttrName() ||
@@ -1543,11 +1544,45 @@ class CIRFuncLowering : public mlir::OpConversionPattern<mlir::cir::FuncOp> {
       if (attr.getName() == func.getExtraAttrsAttrName()) {
         std::string cirName = "cir." + func.getExtraAttrsAttrName().str();
         attr.setName(mlir::StringAttr::get(getContext(), cirName));
+
+        lowerFuncOpenCLKernelMetadata(attr);
       }
       result.push_back(attr);
     }
   }
 
+  /// When do module translation, we can only translate LLVM-compatible types.
+  /// Here we lower possible OpenCLKernelMetadataAttr to use the converted type.
+  void
+  lowerFuncOpenCLKernelMetadata(mlir::NamedAttribute &extraAttrsEntry) const {
+    const auto attrKey = mlir::cir::OpenCLKernelMetadataAttr::getMnemonic();
+    auto oldExtraAttrs =
+        cast<mlir::cir::ExtraFuncAttributesAttr>(extraAttrsEntry.getValue());
+    if (!oldExtraAttrs.getElements().contains(attrKey))
+      return;
+
+    mlir::NamedAttrList newExtraAttrs;
+    for (auto entry : oldExtraAttrs.getElements()) {
+      if (entry.getName() == attrKey) {
+        auto clKernelMetadata =
+            cast<mlir::cir::OpenCLKernelMetadataAttr>(entry.getValue());
+        if (auto vecTypeHint = clKernelMetadata.getVecTypeHint()) {
+          auto newType = typeConverter->convertType(vecTypeHint.getValue());
+          auto newTypeHint = mlir::TypeAttr::get(newType);
+          auto newCLKMAttr = mlir::cir::OpenCLKernelMetadataAttr::get(
+              getContext(), clKernelMetadata.getWorkGroupSizeHint(),
+              clKernelMetadata.getReqdWorkGroupSize(), newTypeHint,
+              clKernelMetadata.getVecTypeHintSignedness(),
+              clKernelMetadata.getIntelReqdSubGroupSize());
+          entry.setValue(newCLKMAttr);
+        }
+      }
+      newExtraAttrs.push_back(entry);
+    }
+    extraAttrsEntry.setValue(mlir::cir::ExtraFuncAttributesAttr::get(
+        getContext(), newExtraAttrs.getDictionary(getContext())));
+  }
+
   mlir::LogicalResult
   matchAndRewrite(mlir::cir::FuncOp op, OpAdaptor adaptor,
                   mlir::ConversionPatternRewriter &rewriter) const override {
@@ -1585,7 +1620,7 @@ class CIRFuncLowering : public mlir::OpConversionPattern<mlir::cir::FuncOp> {
 
     auto linkage = convertLinkage(op.getLinkage());
     SmallVector<mlir::NamedAttribute, 4> attributes;
-    filterFuncAttributes(op, /*filterArgAndResAttrs=*/false, attributes);
+    lowerFuncAttributes(op, /*filterArgAndResAttrs=*/false, attributes);
 
     auto fn = rewriter.create<mlir::LLVM::LLVMFuncOp>(
         Loc, op.getName(), llvmFnTy, linkage, isDsoLocal, mlir::LLVM::CConv::C,