[Moore] Add explicit truncation and zero/sign-extension #7783
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Add the `moore.trunc` operation to explicitly truncate the bit width of `IntType` values, and `moore.zext` and `moore.sext` to explicitly extend such a value with zeroes or its sign bit. This requires tweaking the way how ImportVerilog generates conversion ops. Currently `moore.conversion` is used as a catch-all operation that expresses any kind of type conversion. In the future, we'll want to split this up into multiple dedicated operations. These width adjustment ops are the first step in that direction. Making sign-extension explicit also fixes a long-standing issue where a `$signed` or `signed'(x)` expression would be erroneously converted into a zero-extension.
hailongSun2000
approved these changes
Nov 8, 2024
Comment on lines
+1082
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| if (value.getType() != srcWidthType) | ||
| value = builder.create<moore::ConversionOp>(value.getLoc(), srcWidthType, | ||
| value); |
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Add the
moore.truncoperation to explicitly truncate the bit width ofIntTypevalues, andmoore.zextandmoore.sextto explicitly extend such a value with zeroes or its sign bit.This requires tweaking the way how ImportVerilog generates conversion ops. Currently
moore.conversionis used as a catch-all operation that expresses any kind of type conversion. In the future, we'll want to split this up into multiple dedicated operations. These width adjustment ops are the first step in that direction.Making sign-extension explicit also fixes a long-standing issue where a
$signedorsigned'(x)expression would be erroneously converted into a zero-extension.