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[docs] Remove confusing reset in Seq docs SV example #7419

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Aug 1, 2024
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[docs] Remove confusing reset in Seq docs SV example #7419

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2 changes: 1 addition & 1 deletion docs/Dialects/Seq/RationaleSeq.md
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Original file line number Diff line number Diff line change
Expand Up @@ -146,7 +146,7 @@ Examples of registers:
A register without a reset lowers directly to an always block:

```
always @(posedge clk or [posedge reset]) begin
always @(posedge clk) begin
a <= [%input]
end
```
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