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Move ResetType under the sv namespace #7300

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Jul 10, 2024
Merged

Move ResetType under the sv namespace #7300

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5 changes: 3 additions & 2 deletions include/circt/Dialect/SV/SVStatements.td
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Original file line number Diff line number Diff line change
Expand Up @@ -268,8 +268,9 @@ def SyncReset: I32EnumAttrCase<"SyncReset", 1, "syncreset">;
def AsyncReset: I32EnumAttrCase<"AsyncReset", 2, "asyncreset">;

def ResetTypeAttr : I32EnumAttr<"ResetType", "reset type",
[NoReset, SyncReset, AsyncReset]>;

[NoReset, SyncReset, AsyncReset]> {
let cppNamespace = "::circt::sv";
}

def AlwaysFFOp : SVOp<"alwaysff", [SingleBlock, NoTerminator, NoRegionArguments,
RecursiveMemoryEffects, RecursivelySpeculatable,
Expand Down
12 changes: 6 additions & 6 deletions lib/Conversion/FIRRTLToHW/LowerToHW.cpp
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Expand Up @@ -1467,11 +1467,11 @@ struct FIRRTLLowering : public FIRRTLVisitor<FIRRTLLowering, LogicalResult> {
Value getNonClockValue(Value v);

void addToAlwaysBlock(sv::EventControl clockEdge, Value clock,
::ResetType resetStyle, sv::EventControl resetEdge,
sv::ResetType resetStyle, sv::EventControl resetEdge,
Value reset, std::function<void(void)> body = {},
std::function<void(void)> resetBody = {});
void addToAlwaysBlock(Value clock, std::function<void(void)> body = {}) {
addToAlwaysBlock(sv::EventControl::AtPosEdge, clock, ::ResetType(),
addToAlwaysBlock(sv::EventControl::AtPosEdge, clock, sv::ResetType(),
sv::EventControl(), Value(), body,
std::function<void(void)>());
}
Expand Down Expand Up @@ -1736,7 +1736,7 @@ struct FIRRTLLowering : public FIRRTLVisitor<FIRRTLLowering, LogicalResult> {
// We auto-unique graph-level blocks to reduce the amount of generated
// code and ensure that side effects are properly ordered in FIRRTL.
using AlwaysKeyType = std::tuple<Block *, sv::EventControl, Value,
::ResetType, sv::EventControl, Value>;
sv::ResetType, sv::EventControl, Value>;
llvm::SmallDenseMap<AlwaysKeyType, std::pair<sv::AlwaysOp, sv::IfOp>>
alwaysBlocks;
llvm::SmallDenseMap<std::pair<Block *, Attribute>, sv::IfDefOp> ifdefBlocks;
Expand Down Expand Up @@ -2511,7 +2511,7 @@ Value FIRRTLLowering::getNonClockValue(Value v) {
}

void FIRRTLLowering::addToAlwaysBlock(sv::EventControl clockEdge, Value clock,
::ResetType resetStyle,
sv::ResetType resetStyle,
sv::EventControl resetEdge, Value reset,
std::function<void(void)> body,
std::function<void(void)> resetBody) {
Expand All @@ -2523,7 +2523,7 @@ void FIRRTLLowering::addToAlwaysBlock(sv::EventControl clockEdge, Value clock,

if (!alwaysOp) {
if (reset) {
assert(resetStyle != ::ResetType::NoReset);
assert(resetStyle != sv::ResetType::NoReset);
// Here, we want to create the folloing structure with sv.always and
// sv.if. If `reset` is async, we need to add `reset` to a sensitivity
// list.
Expand All @@ -2542,7 +2542,7 @@ void FIRRTLLowering::addToAlwaysBlock(sv::EventControl clockEdge, Value clock,
insideIfOp = builder.create<sv::IfOp>(
reset, []() {}, []() {});
};
if (resetStyle == ::ResetType::AsyncReset) {
if (resetStyle == sv::ResetType::AsyncReset) {
sv::EventControl events[] = {clockEdge, resetEdge};
Value clocks[] = {clock, reset};

Expand Down
8 changes: 4 additions & 4 deletions lib/Conversion/SeqToSV/FirRegLowering.cpp
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Expand Up @@ -533,7 +533,7 @@ FirRegLowering::RegLowerInfo FirRegLowering::lower(FirRegOp reg) {
else
createTree(b, svReg.reg, reg, reg.getNext());
},
reg.getIsAsync() ? ResetType::AsyncReset : ResetType::SyncReset,
reg.getIsAsync() ? sv::ResetType::AsyncReset : sv::ResetType::SyncReset,
sv::EventControl::AtPosEdge, reg.getReset(),
[&](OpBuilder &builder) {
builder.create<sv::PAssignOp>(loc, svReg.reg, reg.getResetValue());
Expand Down Expand Up @@ -616,7 +616,7 @@ void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg,

void FirRegLowering::addToAlwaysBlock(
Block *block, sv::EventControl clockEdge, Value clock,
const std::function<void(OpBuilder &)> &body, ::ResetType resetStyle,
const std::function<void(OpBuilder &)> &body, sv::ResetType resetStyle,
sv::EventControl resetEdge, Value reset,
const std::function<void(OpBuilder &)> &resetBody) {
auto loc = clock.getLoc();
Expand All @@ -632,7 +632,7 @@ void FirRegLowering::addToAlwaysBlock(

if (!alwaysOp) {
if (reset) {
assert(resetStyle != ::ResetType::NoReset);
assert(resetStyle != sv::ResetType::NoReset);
// Here, we want to create the following structure with sv.always and
// sv.if. If `reset` is async, we need to add `reset` to a sensitivity
// list.
Expand All @@ -651,7 +651,7 @@ void FirRegLowering::addToAlwaysBlock(
insideIfOp = builder.create<sv::IfOp>(
reset, []() {}, []() {});
};
if (resetStyle == ::ResetType::AsyncReset) {
if (resetStyle == sv::ResetType::AsyncReset) {
sv::EventControl events[] = {clockEdge, resetEdge};
Value clocks[] = {clock, reset};

Expand Down
6 changes: 3 additions & 3 deletions lib/Conversion/SeqToSV/FirRegLowering.h
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Expand Up @@ -107,7 +107,7 @@ class FirRegLowering {

void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock,
const std::function<void(OpBuilder &)> &body,
ResetType resetStyle = {},
sv::ResetType resetStyle = {},
sv::EventControl resetEdge = {}, Value reset = {},
const std::function<void(OpBuilder &)> &resetBody = {});

Expand All @@ -127,8 +127,8 @@ class FirRegLowering {
return constant;
}

using AlwaysKeyType = std::tuple<Block *, sv::EventControl, Value, ResetType,
sv::EventControl, Value>;
using AlwaysKeyType = std::tuple<Block *, sv::EventControl, Value,
sv::ResetType, sv::EventControl, Value>;
llvm::SmallDenseMap<AlwaysKeyType, std::pair<sv::AlwaysOp, sv::IfOp>>
alwaysBlocks;

Expand Down
2 changes: 1 addition & 1 deletion lib/Conversion/SeqToSV/SeqToSV.cpp
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Expand Up @@ -97,7 +97,7 @@ class CompRegLower : public OpConversionPattern<OpTy> {
if (lowerToAlwaysFF) {
rewriter.create<sv::AlwaysFFOp>(
loc, sv::EventControl::AtPosEdge, adaptor.getClk(),
ResetType::SyncReset, sv::EventControl::AtPosEdge,
sv::ResetType::SyncReset, sv::EventControl::AtPosEdge,
adaptor.getReset(), assignValue, assignReset);
} else {
rewriter.create<sv::AlwaysOp>(
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/ESI/ESIServices.cpp
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Expand Up @@ -278,7 +278,7 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
// Now construct the memory writes.
auto hwClk = b.create<seq::FromClockOp>(clk);
b.create<sv::AlwaysFFOp>(
sv::EventControl::AtPosEdge, hwClk, ResetType::SyncReset,
sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset,
sv::EventControl::AtPosEdge, rst, [&] {
for (auto [go, address, data] : writeGoAddressData) {
Value a = address, d = data; // So the lambda can capture.
Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/Seq/Transforms/LowerSeqHLMem.cpp
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Expand Up @@ -100,8 +100,8 @@ struct SimpleBehavioralMemoryLowering

auto hwClk = rewriter.create<seq::FromClockOp>(clk.getLoc(), clk);
rewriter.create<sv::AlwaysFFOp>(
mem.getLoc(), sv::EventControl::AtPosEdge, hwClk, ResetType::SyncReset,
sv::EventControl::AtPosEdge, rst, [&] {
mem.getLoc(), sv::EventControl::AtPosEdge, hwClk,
sv::ResetType::SyncReset, sv::EventControl::AtPosEdge, rst, [&] {
for (auto [loc, address, data, en] : writeTuples) {
Value a = address, d = data; // So the lambda can capture.
Location l = loc;
Expand Down
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