[ImportVerilog] Distinguish the index up or down on the range selection.

[hailongSun2000]

For example:

  byte by;
  logic [7:0] b;
  assign by = b[7-:8];

Now:

    %by = moore.variable : <i8>
    %b = moore.variable : <l8>
    %0 = moore.read %b : l8
    %1 = moore.constant 7 : i32

    %2 = moore.constant 7 : i32
    %3 = moore.sub %1, %2 : i32

    %4 = moore.extract %0 from %3 : l8, i32 -> l8              // low bit is "0"
    %5 = moore.conversion %4 : !moore.l8 -> !moore.i8
    moore.assign %by, %5 : i8

---

Previous:

    %by = moore.variable : <i8>
    %b = moore.variable : <l8>
    %0 = moore.read %b : l8

    %1 = moore.constant 7 : i32
    %2 = moore.extract %0 from %1 : l8, i32 -> l8              // low bit is "7";

    %3 = moore.conversion %2 : !moore.l8 -> !moore.i8
    moore.assign %by, %3 : i8

[hailongSun2000]

Before @fabianschuiki refactored the Moore type system, we can get the bits slice range from type, like logic<range<7:0>>, or range<0:7>, or range<2:3>... But now we cannot get this information. From my perspective, the IR after modification is more clear. If it's reasonable, I'll tweak the extract_ref.
If I misunderstand, please teach me about the big and little endian. Thanks in advance.

[fabianschuiki]

Thanks for fixing this! Looks great! 🥳