[FIRRTL][GCT] Add support for tapping non-passive bundles, add test.

[dtzSiFive]

Builds on #4801 .

Relevant commit: c6a7974 .

[dtzSiFive]

Only draft until support piece is in, FWIW.

[dtzSiFive]

Idea is to support what could also be done w/probes. Anyway, this would introduce a difference in behavior regarding what's connectable with and without the hidden --lower-annotations-no-ref-type-ports option enabled, which presently allows taps to be bidirectional:

circuit WiringFlips : %[[
  {
    "class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
    "keys": [
      {
        "class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
        "source": "~WiringFlips|WiringFlips/c:Child>w",
        "sink": "~WiringFlips|WiringFlips>w"
      }
    ]
  }
]]
  module Child :
     output x : UInt<3>
     wire w : { flip x : UInt<3>, y : UInt<4> }
     w.y <= UInt(3)
     x <= w.x

  module WiringFlips :
     input x : UInt<3>
     output y : UInt<4>
     output c_x : UInt<3>

     wire w : { flip x : UInt<3>, y : UInt<4> }
     w.x <= x
     y <= w.y

     inst c of Child
     c_x <= c.x

This probably should be rejected for DataTap's, may make sense for LegacyWiringProblem's that don't have multiple sinks (ambiguous which sink's flipped fields should drive the source)?

[dtzSiFive]

Welp, we presently crash on the above input w/o the hidden flag, so ... progress!

[dtzSiFive]

Can totally support some non-passive sinks (driving all fields individually) in the future, at least as long as it's not a port or something. Don't think it's worth supporting until there's a need/ask.