[RTGTest] Add store instructions (#8118)

include/circt/Dialect/RTGTest/IR/RTGTestOps.td

@@ -231,6 +231,50 @@ class InstFormatROpBase<string mnemonic, int opcode7, int funct3, int funct7>
   }];
 }
 
+class InstFormatSOpBase<string mnemonic, int opcode7, int funct3>
+  : RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {
+
+  let arguments = (ins IntegerRegisterType:$rs1,
+                       IntegerRegisterType:$rs2,
+                       Imm12Type:$imm);
+
+  let assemblyFormat = "$rs1 `,` $rs2 `,` $imm attr-dict";
+
+  let extraClassDefinition = [{
+    void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
+                                           FoldAdaptor adaptor) {
+      auto rs1 = cast<rtg::RegisterAttrInterface>(adaptor.getRs1());
+      auto rs2 = cast<rtg::RegisterAttrInterface>(adaptor.getRs2());
+      auto imm = cast<Imm12Attr>(adaptor.getImm()).getAPInt();
+
+      auto binary = imm.extractBits(7, 5)
+      .concat(llvm::APInt(5, rs2.getClassIndex()))
+      .concat(llvm::APInt(5, rs1.getClassIndex()))
+      .concat(llvm::APInt(3, }] # funct3 # [{))
+      .concat(imm.extractBits(5, 0))
+      .concat(llvm::APInt(7, }] # opcode7 # [{));
+
+      SmallVector<char> str;
+      binary.toStringUnsigned(str, 16);
+      os << str;
+    }
+
+    void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
+                                             FoldAdaptor adaptor) {
+      os << getOperationName().rsplit('.').second
+         << " "
+         << cast<rtg::RegisterAttrInterface>(adaptor.getRs1())
+              .getRegisterAssembly()
+         << ", "
+         << cast<Imm12Attr>(adaptor.getImm()).getValue()
+         << "("
+         << cast<rtg::RegisterAttrInterface>(adaptor.getRs2())
+              .getRegisterAssembly()
+         << ")";
+    }
+  }];
+}
+
 //===- Instructions -------------------------------------------------------===//
 
 def RV32I_JALROp    : InstFormatIOpBase<"jalr",  0b1100111, 0b000>;
@@ -248,6 +292,10 @@ def RV32I_LWOp      : InstFormatIOpBase<"lw",  0b0000011, 0b010>;
 def RV32I_LBUOp     : InstFormatIOpBase<"lbu", 0b0000011, 0b100>;
 def RV32I_LHUOp     : InstFormatIOpBase<"lhu", 0b0000011, 0b101>;
 
+def RV32I_SB        : InstFormatSOpBase<"sb", 0b0100011, 0b000>;
+def RV32I_SH        : InstFormatSOpBase<"sh", 0b0100011, 0b001>;
+def RV32I_SW        : InstFormatSOpBase<"sw", 0b0100011, 0b010>;
+
 def RV32I_ADD       : InstFormatROpBase<"add",  0b110011, 0b000, 0b0000000>;
 def RV32I_SUB       : InstFormatROpBase<"sub",  0b110011, 0b000, 0b0100000>;
 def RV32I_SLL       : InstFormatROpBase<"sll",  0b110011, 0b001, 0b0000000>;

test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir

@@ -131,6 +131,21 @@ rtg.test @test0 : !rtg.dict<> {
   // CHECK-NEXT:    # and ra, s0, s0
   // CHECK-NEXT:    .word 0x8470B3
   rtgtest.rv32i.and %rd, %rs, %rs
+
+  // CHECK-ALLOWED-NEXT:    sb ra, 0(s0)
+  // CHECK-NEXT:    # sb ra, 0(s0)
+  // CHECK-NEXT:    .word 0x808023
+  rtgtest.rv32i.sb %rd, %rs, %imm
+
+  // CHECK-ALLOWED-NEXT:    sh ra, 0(s0)
+  // CHECK-NEXT:    # sh ra, 0(s0)
+  // CHECK-NEXT:    .word 0x809023
+  rtgtest.rv32i.sh %rd, %rs, %imm
+
+  // CHECK-ALLOWED-NEXT:    sw ra, 0(s0)
+  // CHECK-NEXT:    # sw ra, 0(s0)
+  // CHECK-NEXT:    .word 0x80A023
+  rtgtest.rv32i.sw %rd, %rs, %imm
 }
 
 // CHECK-EMPTY:

test/Dialect/RTG/Transform/unsupported-instr.txt

@@ -1 +1 @@
-rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and
+rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and,rtgtest.rv32i.sb,rtgtest.rv32i.sh,rtgtest.rv32i.sw

test/Dialect/RTGTest/IR/basic.mlir

@@ -163,6 +163,13 @@ rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, imm13: !rtgtest.imm13, l
   rtgtest.rv32i.or %rd, %rs, %rs {rtg.some_attr}
   // CHECK: rtgtest.rv32i.and [[RD]], [[RS]], [[RS]] {rtg.some_attr}
   rtgtest.rv32i.and %rd, %rs, %rs {rtg.some_attr}
+
+  // CHECK: rtgtest.rv32i.sb [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
+  rtgtest.rv32i.sb %rd, %rs, %imm {rtg.some_attr}
+  // CHECK: rtgtest.rv32i.sh [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
+  rtgtest.rv32i.sh %rd, %rs, %imm {rtg.some_attr}
+  // CHECK: rtgtest.rv32i.sw [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
+  rtgtest.rv32i.sw %rd, %rs, %imm {rtg.some_attr}
 }
 
 // -----