Feature/risc v debugging #1
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This can be used to access a PE over JTAG
A visible JTAG over AXI module created problems while executing RISC-V code
Can be treated as a normal peripheral reset and does not need to be supported bei converter
Also connects clk and rst to jtag switch
Converter now also supports the usage of the JTAG chain.
The name: JtagDebug Options: enabled: true | false device_type: jtag_switch | jtag_chain
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Including: * Activate * Halt/Resume * Read registers * Read/write memory
…re/RISC-V-Debugging
* This example can now open a Unix socket. * OpenOCD connects to Unix Socket * Communication between those two is done with cap'n proto
The DebugGenerator for RISC-V is now in the riscvdebugging GitLab repository as a library.
The latter one creates one AXI-to-JTAG module and the JTAG signal is multiplexed by a JTAG splitter
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Implementation of Debugging Support into TaPaSCo for a Heterogeneous RISC-V System