Promote shift RHS to vectors if needed

Fixes ldc-developers#3606.
kinke · Nov 13, 2024 · eefe08d · eefe08d
1 parent c32c7ee
commit eefe08d
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Showing 3 changed files with 18 additions and 68 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -14,6 +14,7 @@
 - Fix potentially corrupt IR layouts for bit fields. (#4646, #4708)
 - Fix potentially corrupt IR layouts for explicitly under-aligned aggregates, a regression introduced in LDC v1.31. (#4734, #4736)
 - ELF: Emit (most) instantiated symbols in COMDATs for proper link-time culling. (#3589, #4748)
+- Support scalar right-hand-sides when bit-shifting vectors. (#3606, #4781)
 
 # LDC 1.39.0 (2024-07-04)
 

diff --git a/dmd/expressionsem.d b/dmd/expressionsem.d
@@ -13016,9 +13016,8 @@ version (IN_LLVM)
         return;
     }
 
-    override void visit(ShlExp exp)
+    private void visitShiftExp(BinExp exp)
     {
-        //printf("ShlExp::semantic(), type = %p\n", type);
         if (exp.type)
         {
             result = exp;
@@ -13045,84 +13044,29 @@ version (IN_LLVM)
             result = exp.incompatibleTypes();
             return;
         }
+
         exp.e1 = integralPromotions(exp.e1, sc);
         if (exp.e2.type.toBasetype().ty != Tvector)
-            exp.e2 = exp.e2.castTo(sc, Type.tshiftcnt);
+        {
+            Type tb1 = exp.e1.type.toBasetype();
+            exp.e2 = exp.e2.castTo(sc, tb1.ty == Tvector ? tb1 : Type.tshiftcnt);
+        }
 
         exp.type = exp.e1.type;
         result = exp;
     }
 
+    override void visit(ShlExp exp)
+    {
+        visitShiftExp(exp);
+    }
     override void visit(ShrExp exp)
     {
-        if (exp.type)
-        {
-            result = exp;
-            return;
-        }
-
-        if (Expression ex = binSemanticProp(exp, sc))
-        {
-            result = ex;
-            return;
-        }
-        Expression e = exp.op_overload(sc);
-        if (e)
-        {
-            result = e;
-            return;
-        }
-
-        if (exp.checkIntegralBin() || exp.checkSharedAccessBin(sc))
-            return setError();
-
-        if (!target.isVectorOpSupported(exp.e1.type.toBasetype(), exp.op, exp.e2.type.toBasetype()))
-        {
-            result = exp.incompatibleTypes();
-            return;
-        }
-        exp.e1 = integralPromotions(exp.e1, sc);
-        if (exp.e2.type.toBasetype().ty != Tvector)
-            exp.e2 = exp.e2.castTo(sc, Type.tshiftcnt);
-
-        exp.type = exp.e1.type;
-        result = exp;
+        visitShiftExp(exp);
     }
-
     override void visit(UshrExp exp)
     {
-        if (exp.type)
-        {
-            result = exp;
-            return;
-        }
-
-        if (Expression ex = binSemanticProp(exp, sc))
-        {
-            result = ex;
-            return;
-        }
-        Expression e = exp.op_overload(sc);
-        if (e)
-        {
-            result = e;
-            return;
-        }
-
-        if (exp.checkIntegralBin() || exp.checkSharedAccessBin(sc))
-            return setError();
-
-        if (!target.isVectorOpSupported(exp.e1.type.toBasetype(), exp.op, exp.e2.type.toBasetype()))
-        {
-            result = exp.incompatibleTypes();
-            return;
-        }
-        exp.e1 = integralPromotions(exp.e1, sc);
-        if (exp.e2.type.toBasetype().ty != Tvector)
-            exp.e2 = exp.e2.castTo(sc, Type.tshiftcnt);
-
-        exp.type = exp.e1.type;
-        result = exp;
+        visitShiftExp(exp);
     }
 
     override void visit(AndExp exp)

diff --git a/tests/codegen/vector_ops.d b/tests/codegen/vector_ops.d
@@ -44,6 +44,11 @@ void main()
 
     const int4 i = [ 1, 2, 3, 4 ];
     assert(i << i is [ 2, 8, 24, 64 ]);
+    assert(i << 2 is [ 4, 8, 12, 16 ]);
+    assert(i >> int4(1) is [ 0, 1, 1, 2 ]);
+    assert(i >> 1 is [ 0, 1, 1, 2 ]);
+    assert(i >>> int4(1) is [ 0, 1, 1, 2 ]);
+    assert(i >>> 1 is [ 0, 1, 1, 2 ]);
 
     const int4 a = [ 0b1, 0b10, 0b101, 0b100011 ];
     const int4 b = 0b110;