Skip to content

Commit

Permalink
Clean up code and comments a little.
Browse files Browse the repository at this point in the history
  • Loading branch information
@keirf
keirf committed Dec 17, 2019
1 parent f2239d4 commit c15df04
Show file tree
Hide file tree
Showing 2 changed files with 39 additions and 34 deletions.
15 changes: 8 additions & 7 deletions src/config.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,10 +22,8 @@ extern void setup_spi(uint16_t video_mode);
extern uint16_t running_polarity;
extern uint16_t running_display_timing;

const static char *dispen_pretty[] = { "None", "PA15 Act.HIGH", "PA15 Act.LOW" };
/* PB15 is tristate outside OSD; PA15 unused
* PA15 is Display Enable: Active HIGH
* PA15 is Display Enable: Active LOW */
const static char *dispen_pretty[] = {
"None", "PA15 Act.HIGH", "PA15 Act.LOW" };

const static char *timing_pretty[] = { "15kHz", "VGA", "Auto" };

Expand All @@ -37,7 +35,8 @@ static void config_printk(const struct config *conf)
printk(" Sync Polarity: %s\n", polarity_pretty[conf->polarity]);
printk(" Pixel Timing: %s\n", timing_pretty[config.display_timing]);
printk(" Display Height: %s\n", conf->display_2Y ? "Double" : "Normal");
printk(" Display Output: %s\n", config.display_spi ? "PA7/SPI1" : "PB15/SPI2");
printk(" Display Output: %s\n",
config.display_spi ? "PA7/SPI1" : "PB15/SPI2");
printk(" Display Enable: %s\n", dispen_pretty[config.dispctl_mode] );
printk(" H.Off: %u\n", conf->h_off);
printk(" V.Off: %u\n", conf->v_off);
Expand Down Expand Up @@ -248,7 +247,8 @@ void config_process(uint8_t b, bool_t autosync_changed)
}
if (b || autosync_changed) {
if (config.polarity == SYNC_AUTO)
cnf_prt(1, "%s (%s)", polarity_pretty[config.polarity], polarity_pretty[running_polarity]);
cnf_prt(1, "%s (%s)", polarity_pretty[config.polarity],
polarity_pretty[running_polarity]);
else
cnf_prt(1, "%s", polarity_pretty[config.polarity]);
}
Expand All @@ -272,7 +272,8 @@ void config_process(uint8_t b, bool_t autosync_changed)
}
if (b || autosync_changed) {
if (config.display_timing == DISP_AUTO)
cnf_prt(1, "%s (%s)", timing_pretty[config.display_timing], timing_pretty[running_display_timing]);
cnf_prt(1, "%s (%s)", timing_pretty[config.display_timing],
timing_pretty[running_display_timing]);
else
cnf_prt(1, "%s", timing_pretty[config.display_timing]);
}
Expand Down
58 changes: 31 additions & 27 deletions src/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -261,20 +261,16 @@ static void slave_arr_update(void)
vstart = config.v_off*2;
if (startup_display_spi == DISP_SPI1) {
hstart = config.h_off * 7;

/* Enable output pin first (TIM4) and then start SPI transfers (TIM2).
* timers run at 72 MHz, pixel clock is 36 MHz, 2 count per pixel
* (13-1)/2 = 6 pixel
*/
/* Enable output pin first (TIM4) and then start SPI transfers
* (TIM2). Timers run at 72 MHz, pixel clock is 36 MHz, 2 ticks
* per pixel: (13-1)/2 = 6 pixel */
tim4->arr = hstart-12;
tim2->arr = hstart-1;
} else {
hstart = config.h_off * 7;

/* Enable output pin first (TIM4) and then start SPI transfers (TIM2).
* timers run at 72 MHz, pixel clock is 18 MHz, 4 count per pixel
* (25-1)/4 = 6 pixel
*/
/* Enable output pin first (TIM4) and then start SPI transfers
* (TIM2). Timers run at 72 MHz, pixel clock is 18 MHz, 4 ticks
* per pixel: (25-1)/4 = 6 pixel */
tim4->arr = hstart-24;
tim2->arr = hstart-1;
}
Expand All @@ -284,10 +280,9 @@ static void slave_arr_update(void)
default:
vstart = config.v_off;
hstart = config.h_off * 20;

/* Enable output pin first (TIM4) and then start SPI transfers (TIM2).
* timers run at 72 MHz, pixel clock is 9 MHz, 8 count per pixel
* (49-1)/8 = 6 pixel */
/* Enable output pin first (TIM4) and then start SPI transfers
* (TIM2). Timers run at 72 MHz, pixel clock is 9 MHz, 8 ticks per
* pixel: (49-1)/8 = 6 pixel */
tim4->arr = hstart-49;
tim2->arr = hstart-1;
break;
Expand Down Expand Up @@ -443,37 +438,46 @@ static void setup_dispctl_mode(void)

case DISPCTL_tristate:
/* PA15: Unused
* PB15: Tristate outside OSD box */
* SPIx: Tristate outside OSD box */

if (startup_display_spi == DISP_SPI1)
{ // PA7 SPI1
gpio_configure_pin(gpio_display_spi1, pin_display_spi1, GPI_floating);
if (startup_display_spi == DISP_SPI1) {
/* PA7, SPI1 */
gpio_configure_pin(gpio_display_spi1, pin_display_spi1,
GPI_floating);
dispctl_reg = (uint32_t)(unsigned long)&gpio_display_spi1->crl;
gpio_configure_pin(gpio_display_spi1, pin_display_spi1, AFO_pushpull(_50MHz));
gpio_configure_pin(gpio_display_spi1, pin_display_spi1,
AFO_pushpull(_50MHz));
dispctl_on = gpio_display_spi1->crl;
gpio_configure_pin(gpio_display_spi1, pin_display_spi1, GPI_floating);
gpio_configure_pin(gpio_display_spi1, pin_display_spi1,
GPI_floating);
dispctl_off = gpio_display_spi1->crl;

} else { // PB15 SPI2
gpio_configure_pin(gpio_display_spi2, pin_display_spi2, GPI_floating);
} else {
/* PB15, SPI2 */
gpio_configure_pin(gpio_display_spi2, pin_display_spi2,
GPI_floating);
dispctl_reg = (uint32_t)(unsigned long)&gpio_display_spi2->crh;
gpio_configure_pin(gpio_display_spi2, pin_display_spi2, AFO_pushpull(_50MHz));
gpio_configure_pin(gpio_display_spi2, pin_display_spi2,
AFO_pushpull(_50MHz));
dispctl_on = gpio_display_spi2->crh;
gpio_configure_pin(gpio_display_spi2, pin_display_spi2, GPI_floating);
gpio_configure_pin(gpio_display_spi2, pin_display_spi2,
GPI_floating);
dispctl_off = gpio_display_spi2->crh;
}
break;

case DISPCTL_enable_high:
case DISPCTL_enable_low: {
/* PA15: Display Enable: Active HIGH or LOW
* PB15: Always driven */
* SPIx: Always driven */
bool_t active_low = (startup_dispctl_mode == DISPCTL_enable_low);

if (startup_display_spi == DISP_SPI1) {
gpio_configure_pin(gpio_display_spi1, pin_display_spi1, AFO_pushpull(_50MHz));
gpio_configure_pin(gpio_display_spi1, pin_display_spi1,
AFO_pushpull(_50MHz));
} else {
gpio_configure_pin(gpio_display_spi2, pin_display_spi2, AFO_pushpull(_50MHz));
gpio_configure_pin(gpio_display_spi2, pin_display_spi2,
AFO_pushpull(_50MHz));
}

gpio_configure_pin(gpio_dispen, pin_dispen,
Expand Down

0 comments on commit c15df04

Please sign in to comment.