CPUDesignProject

Implementation of a simple RISC style processor for on an Altera DE0 Cyclone III board. Created using VHDL and Altera Quartus II. Project created for course project in ELEC 374 Computer Architecture course at Queen's University.

Getting Started

These instructions will get you a copy of the project up and running on your local machine for development and testing purposes. See deployment for notes on how to deploy the project on a live system.

Prerequisites

What things you need to install the software and how to install them

Altera Quartus II
Model Sim Altera Quartus Addon
Altera DE0 board (not required for only simulation activities)

How to open project

Start Altera Quartus II
Open SRC_CPU.qpf project file
Investigate VHDL contents for each component of the CPU.
1. Example, workingBooth.vhd implements the Booth's multiplication algorithm.
2. Another example, datapath.vhd combines all components required for the CPU's datapath.
Use ModelSim to simulate various CPU functions. Image below shows a shift right register simulation (Other screenshots can be found in Simulation_Pictures directory).

Authors

Madeline Van Der Paelt
Maytha Nassor
Johan Cornelissen

Acknowledgments

Prof. Ahmad Afsahi, Instructor of ELEC 374 Computer Architecture during Winter 2016.

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
Simulation_Pictures		Simulation_Pictures
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
.DS_Store		.DS_Store
512_Mem.vhd.bak		512_Mem.vhd.bak
ALU_Toplevel.vhd		ALU_Toplevel.vhd
ALU_Toplevel.vhd.bak		ALU_Toplevel.vhd.bak
ALU_tb.vhd		ALU_tb.vhd
ALU_tb.vhd.bak		ALU_tb.vhd.bak
Bus.bdf		Bus.bdf
Bus.vhd		Bus.vhd
CPU_Bus.bdf		CPU_Bus.bdf
CPU_Bus.vhd		CPU_Bus.vhd
CPU_Bus_Redesign.vhd		CPU_Bus_Redesign.vhd
CPU_Bus_Redesign.vhd.bak		CPU_Bus_Redesign.vhd.bak
CPU_Bus_tb.vhd		CPU_Bus_tb.vhd
CPU_Bus_tb.vhd.bak		CPU_Bus_tb.vhd.bak
ConFF.vhd		ConFF.vhd
ConFF.vhd.bak		ConFF.vhd.bak
DE0_board.vhd		DE0_board.vhd
DE0_board.vhd.bak		DE0_board.vhd.bak
Decoder2to4.cmp		Decoder2to4.cmp
Decoder2to4.qip		Decoder2to4.qip
Decoder2to4.vhd		Decoder2to4.vhd
FA.cmp		FA.cmp
FA.qip		FA.qip
FA.vhd		FA.vhd
FA.vhd.bak		FA.vhd.bak
IRreg.vhd		IRreg.vhd
IRreg.vhd.bak		IRreg.vhd.bak
MDR_Unit.bdf		MDR_Unit.bdf
MDR_Unit.bsf		MDR_Unit.bsf
MDR_Unit.vhd		MDR_Unit.vhd
MDR_Unit.vhd.bak		MDR_Unit.vhd.bak
PCincr.cmp		PCincr.cmp
PCincr.qip		PCincr.qip
PCincr.vhd		PCincr.vhd
README.md		README.md
REG32.bsf		REG32.bsf
REG32.vhd		REG32.vhd
REG32.vhd.bak		REG32.vhd.bak
REG64.vhd		REG64.vhd
REG64.vhd.bak		REG64.vhd.bak
RegSpecial0.vhd		RegSpecial0.vhd
RegSpecial0.vhd.bak		RegSpecial0.vhd.bak
SRC_CPU.qpf		SRC_CPU.qpf
SRC_CPU.qsf		SRC_CPU.qsf
SRC_CPU.qws		SRC_CPU.qws
SRC_CPU.tis_db_list.ddb		SRC_CPU.tis_db_list.ddb
SRC_CPU_nativelink_simulation.rpt		SRC_CPU_nativelink_simulation.rpt
Seven_Segment.vhd		Seven_Segment.vhd
Seven_Segment.vhd.bak		Seven_Segment.vhd.bak
add.cmp		add.cmp
add.qip		add.qip
add.vhd		add.vhd
add_sub.cmp		add_sub.cmp
add_sub.qip		add_sub.qip
add_sub.vhd		add_sub.vhd
add_tb.vhd		add_tb.vhd
add_tb.vhd.bak		add_tb.vhd.bak
and_tb.vhd		and_tb.vhd
and_tb.vhd.bak		and_tb.vhd.bak
array_mult.vhd		array_mult.vhd
array_mult.vhd.bak		array_mult.vhd.bak
boothJohu.vhd		boothJohu.vhd
boothJohu.vhd.bak		boothJohu.vhd.bak
bus_tb.vhd		bus_tb.vhd
bus_tb.vhd.bak		bus_tb.vhd.bak
common.vhd		common.vhd
common.vhd.bak		common.vhd.bak
control_unit.vhd		control_unit.vhd
control_unit.vhd.bak		control_unit.vhd.bak
datapath.vhd		datapath.vhd
datapath.vhd.bak		datapath.vhd.bak
datapath_tb.vhd		datapath_tb.vhd
datapath_tb.vhd.bak		datapath_tb.vhd.bak
decoder.bdf		decoder.bdf
decoder.vhd		decoder.vhd
decoder4to16.vhd		decoder4to16.vhd
decoder4to16.vhd.bak		decoder4to16.vhd.bak
div_tb.vhd		div_tb.vhd
div_tb.vhd.bak		div_tb.vhd.bak
fa1.bsf		fa1.bsf
fa1.cmp		fa1.cmp
fa1.qip		fa1.qip
fa1.vhd		fa1.vhd
fa1.vhd.bak		fa1.vhd.bak
iplauncher_debug.log		iplauncher_debug.log
lpm_decode0.bsf		lpm_decode0.bsf
lpm_decode0.cmp		lpm_decode0.cmp
lpm_decode0.qip		lpm_decode0.qip
lpm_decode0.vhd		lpm_decode0.vhd
lpm_encoder.bsf		lpm_encoder.bsf
lpm_encoder.vhd		lpm_encoder.vhd
lpm_encoder.vhd.bak		lpm_encoder.vhd.bak
lpm_mux0.bsf		lpm_mux0.bsf
lpm_mux0.cmp		lpm_mux0.cmp

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