Senior design project by John Taylor, Preeti Chitre, Fabian Rosadi and Joel Montes de Oca in the Electrical and Computer Engineering Department of California State Polytechnic University at Pomona. The project was completed and demonstrated in May, 2001 at the Cal Poly Pomona College of Engineering Project Symposium,
The project team was presented with criteria and specifications for a design of a simple RISC processor to be implemented on a Spartan 3E FPGA. The project was overseen by faculty advisor Wendy K. Wanderman.