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[Clang][XTHeadVector] add vlmul_trunc and vlmul_ext (ruyisdk#118)
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* [Clang][XTHeadVector] add `vlmul_trunc` and `vlmul_ext` misc intrinsics

* [Clang][XTHeadVector] test `vlmul_trunc` and `vlmul_ext` misc intrinsics

* [Clang][XTHeadVector] wrappers for `vlmul_trunc` and `vlmul_ext` misc intrinsics
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@imkiva
imkiva committed Feb 26, 2025
1 parent 38177bf commit aa8bfb2
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35 changes: 35 additions & 0 deletions clang/include/clang/Basic/riscv_vector_xtheadv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1894,6 +1894,41 @@ let HasMasked = false, HasVL = false, IRName = "" in {
def th_vundefined : RVVBuiltin<"v", "v", "csilxfd">;
def th_vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">;
}

// LMUL truncation
// C/C++ Operand: VecTy, IR Operand: VecTy, Index
let Name = "th_vlmul_trunc_v", OverloadedName = "th_vlmul_trunc",
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{ {
return Builder.CreateExtractVector(ResultType, Ops[0],
ConstantInt::get(Int64Ty, 0));
} }] in {
// no LMUL=8 vector in result value
foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
def th_vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def th_vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
}
}

// LMUL extension
// C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
let Name = "th_vlmul_ext_v", OverloadedName = "th_vlmul_ext",
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
return Builder.CreateInsertVector(ResultType,
llvm::PoisonValue::get(ResultType),
Ops[0], ConstantInt::get(Int64Ty, 0));
}] in {
// no LMUL=1 vector in result value
foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
def th_vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def th_vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
}
}
}

include "riscv_vector_xtheadv_wrappers.td"
133 changes: 133 additions & 0 deletions clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6494,5 +6494,138 @@ let HeaderCode = [{
#define __riscv_vreinterpret_v_u64m1_b8(src) __riscv_th_vreinterpret_v_u64m1_b8(src)
#define __riscv_vreinterpret_v_b8_u64m1(src) __riscv_th_vreinterpret_v_b8_u64m1(src)

#define __riscv_vlmul_ext_v_f16m1_f16m2(op1) __riscv_th_vlmul_ext_v_f16m1_f16m2(op1)
#define __riscv_vlmul_ext_v_f16m1_f16m4(op1) __riscv_th_vlmul_ext_v_f16m1_f16m4(op1)
#define __riscv_vlmul_ext_v_f16m1_f16m8(op1) __riscv_th_vlmul_ext_v_f16m1_f16m8(op1)
#define __riscv_vlmul_ext_v_f16m2_f16m4(op1) __riscv_th_vlmul_ext_v_f16m2_f16m4(op1)
#define __riscv_vlmul_ext_v_f16m2_f16m8(op1) __riscv_th_vlmul_ext_v_f16m2_f16m8(op1)
#define __riscv_vlmul_ext_v_f16m4_f16m8(op1) __riscv_th_vlmul_ext_v_f16m4_f16m8(op1)
#define __riscv_vlmul_ext_v_f32m1_f32m2(op1) __riscv_th_vlmul_ext_v_f32m1_f32m2(op1)
#define __riscv_vlmul_ext_v_f32m1_f32m4(op1) __riscv_th_vlmul_ext_v_f32m1_f32m4(op1)
#define __riscv_vlmul_ext_v_f32m1_f32m8(op1) __riscv_th_vlmul_ext_v_f32m1_f32m8(op1)
#define __riscv_vlmul_ext_v_f32m2_f32m4(op1) __riscv_th_vlmul_ext_v_f32m2_f32m4(op1)
#define __riscv_vlmul_ext_v_f32m2_f32m8(op1) __riscv_th_vlmul_ext_v_f32m2_f32m8(op1)
#define __riscv_vlmul_ext_v_f32m4_f32m8(op1) __riscv_th_vlmul_ext_v_f32m4_f32m8(op1)
#define __riscv_vlmul_ext_v_f64m1_f64m2(op1) __riscv_th_vlmul_ext_v_f64m1_f64m2(op1)
#define __riscv_vlmul_ext_v_f64m1_f64m4(op1) __riscv_th_vlmul_ext_v_f64m1_f64m4(op1)
#define __riscv_vlmul_ext_v_f64m1_f64m8(op1) __riscv_th_vlmul_ext_v_f64m1_f64m8(op1)
#define __riscv_vlmul_ext_v_f64m2_f64m4(op1) __riscv_th_vlmul_ext_v_f64m2_f64m4(op1)
#define __riscv_vlmul_ext_v_f64m2_f64m8(op1) __riscv_th_vlmul_ext_v_f64m2_f64m8(op1)
#define __riscv_vlmul_ext_v_f64m4_f64m8(op1) __riscv_th_vlmul_ext_v_f64m4_f64m8(op1)
#define __riscv_vlmul_ext_v_i8m1_i8m2(op1) __riscv_th_vlmul_ext_v_i8m1_i8m2(op1)
#define __riscv_vlmul_ext_v_i8m1_i8m4(op1) __riscv_th_vlmul_ext_v_i8m1_i8m4(op1)
#define __riscv_vlmul_ext_v_i8m1_i8m8(op1) __riscv_th_vlmul_ext_v_i8m1_i8m8(op1)
#define __riscv_vlmul_ext_v_i8m2_i8m4(op1) __riscv_th_vlmul_ext_v_i8m2_i8m4(op1)
#define __riscv_vlmul_ext_v_i8m2_i8m8(op1) __riscv_th_vlmul_ext_v_i8m2_i8m8(op1)
#define __riscv_vlmul_ext_v_i8m4_i8m8(op1) __riscv_th_vlmul_ext_v_i8m4_i8m8(op1)
#define __riscv_vlmul_ext_v_i16m1_i16m2(op1) __riscv_th_vlmul_ext_v_i16m1_i16m2(op1)
#define __riscv_vlmul_ext_v_i16m1_i16m4(op1) __riscv_th_vlmul_ext_v_i16m1_i16m4(op1)
#define __riscv_vlmul_ext_v_i16m1_i16m8(op1) __riscv_th_vlmul_ext_v_i16m1_i16m8(op1)
#define __riscv_vlmul_ext_v_i16m2_i16m4(op1) __riscv_th_vlmul_ext_v_i16m2_i16m4(op1)
#define __riscv_vlmul_ext_v_i16m2_i16m8(op1) __riscv_th_vlmul_ext_v_i16m2_i16m8(op1)
#define __riscv_vlmul_ext_v_i16m4_i16m8(op1) __riscv_th_vlmul_ext_v_i16m4_i16m8(op1)
#define __riscv_vlmul_ext_v_i32m1_i32m2(op1) __riscv_th_vlmul_ext_v_i32m1_i32m2(op1)
#define __riscv_vlmul_ext_v_i32m1_i32m4(op1) __riscv_th_vlmul_ext_v_i32m1_i32m4(op1)
#define __riscv_vlmul_ext_v_i32m1_i32m8(op1) __riscv_th_vlmul_ext_v_i32m1_i32m8(op1)
#define __riscv_vlmul_ext_v_i32m2_i32m4(op1) __riscv_th_vlmul_ext_v_i32m2_i32m4(op1)
#define __riscv_vlmul_ext_v_i32m2_i32m8(op1) __riscv_th_vlmul_ext_v_i32m2_i32m8(op1)
#define __riscv_vlmul_ext_v_i32m4_i32m8(op1) __riscv_th_vlmul_ext_v_i32m4_i32m8(op1)
#define __riscv_vlmul_ext_v_i64m1_i64m2(op1) __riscv_th_vlmul_ext_v_i64m1_i64m2(op1)
#define __riscv_vlmul_ext_v_i64m1_i64m4(op1) __riscv_th_vlmul_ext_v_i64m1_i64m4(op1)
#define __riscv_vlmul_ext_v_i64m1_i64m8(op1) __riscv_th_vlmul_ext_v_i64m1_i64m8(op1)
#define __riscv_vlmul_ext_v_i64m2_i64m4(op1) __riscv_th_vlmul_ext_v_i64m2_i64m4(op1)
#define __riscv_vlmul_ext_v_i64m2_i64m8(op1) __riscv_th_vlmul_ext_v_i64m2_i64m8(op1)
#define __riscv_vlmul_ext_v_i64m4_i64m8(op1) __riscv_th_vlmul_ext_v_i64m4_i64m8(op1)
#define __riscv_vlmul_ext_v_u8m1_u8m2(op1) __riscv_th_vlmul_ext_v_u8m1_u8m2(op1)
#define __riscv_vlmul_ext_v_u8m1_u8m4(op1) __riscv_th_vlmul_ext_v_u8m1_u8m4(op1)
#define __riscv_vlmul_ext_v_u8m1_u8m8(op1) __riscv_th_vlmul_ext_v_u8m1_u8m8(op1)
#define __riscv_vlmul_ext_v_u8m2_u8m4(op1) __riscv_th_vlmul_ext_v_u8m2_u8m4(op1)
#define __riscv_vlmul_ext_v_u8m2_u8m8(op1) __riscv_th_vlmul_ext_v_u8m2_u8m8(op1)
#define __riscv_vlmul_ext_v_u8m4_u8m8(op1) __riscv_th_vlmul_ext_v_u8m4_u8m8(op1)
#define __riscv_vlmul_ext_v_u16m1_u16m2(op1) __riscv_th_vlmul_ext_v_u16m1_u16m2(op1)
#define __riscv_vlmul_ext_v_u16m1_u16m4(op1) __riscv_th_vlmul_ext_v_u16m1_u16m4(op1)
#define __riscv_vlmul_ext_v_u16m1_u16m8(op1) __riscv_th_vlmul_ext_v_u16m1_u16m8(op1)
#define __riscv_vlmul_ext_v_u16m2_u16m4(op1) __riscv_th_vlmul_ext_v_u16m2_u16m4(op1)
#define __riscv_vlmul_ext_v_u16m2_u16m8(op1) __riscv_th_vlmul_ext_v_u16m2_u16m8(op1)
#define __riscv_vlmul_ext_v_u16m4_u16m8(op1) __riscv_th_vlmul_ext_v_u16m4_u16m8(op1)
#define __riscv_vlmul_ext_v_u32m1_u32m2(op1) __riscv_th_vlmul_ext_v_u32m1_u32m2(op1)
#define __riscv_vlmul_ext_v_u32m1_u32m4(op1) __riscv_th_vlmul_ext_v_u32m1_u32m4(op1)
#define __riscv_vlmul_ext_v_u32m1_u32m8(op1) __riscv_th_vlmul_ext_v_u32m1_u32m8(op1)
#define __riscv_vlmul_ext_v_u32m2_u32m4(op1) __riscv_th_vlmul_ext_v_u32m2_u32m4(op1)
#define __riscv_vlmul_ext_v_u32m2_u32m8(op1) __riscv_th_vlmul_ext_v_u32m2_u32m8(op1)
#define __riscv_vlmul_ext_v_u32m4_u32m8(op1) __riscv_th_vlmul_ext_v_u32m4_u32m8(op1)
#define __riscv_vlmul_ext_v_u64m1_u64m2(op1) __riscv_th_vlmul_ext_v_u64m1_u64m2(op1)
#define __riscv_vlmul_ext_v_u64m1_u64m4(op1) __riscv_th_vlmul_ext_v_u64m1_u64m4(op1)
#define __riscv_vlmul_ext_v_u64m1_u64m8(op1) __riscv_th_vlmul_ext_v_u64m1_u64m8(op1)
#define __riscv_vlmul_ext_v_u64m2_u64m4(op1) __riscv_th_vlmul_ext_v_u64m2_u64m4(op1)
#define __riscv_vlmul_ext_v_u64m2_u64m8(op1) __riscv_th_vlmul_ext_v_u64m2_u64m8(op1)
#define __riscv_vlmul_ext_v_u64m4_u64m8(op1) __riscv_th_vlmul_ext_v_u64m4_u64m8(op1)
#define __riscv_vlmul_trunc_v_f16m2_f16m1(op1) __riscv_th_vlmul_trunc_v_f16m2_f16m1(op1)
#define __riscv_vlmul_trunc_v_f16m4_f16m1(op1) __riscv_th_vlmul_trunc_v_f16m4_f16m1(op1)
#define __riscv_vlmul_trunc_v_f16m4_f16m2(op1) __riscv_th_vlmul_trunc_v_f16m4_f16m2(op1)
#define __riscv_vlmul_trunc_v_f16m8_f16m1(op1) __riscv_th_vlmul_trunc_v_f16m8_f16m1(op1)
#define __riscv_vlmul_trunc_v_f16m8_f16m2(op1) __riscv_th_vlmul_trunc_v_f16m8_f16m2(op1)
#define __riscv_vlmul_trunc_v_f16m8_f16m4(op1) __riscv_th_vlmul_trunc_v_f16m8_f16m4(op1)
#define __riscv_vlmul_trunc_v_f32m2_f32m1(op1) __riscv_th_vlmul_trunc_v_f32m2_f32m1(op1)
#define __riscv_vlmul_trunc_v_f32m4_f32m1(op1) __riscv_th_vlmul_trunc_v_f32m4_f32m1(op1)
#define __riscv_vlmul_trunc_v_f32m4_f32m2(op1) __riscv_th_vlmul_trunc_v_f32m4_f32m2(op1)
#define __riscv_vlmul_trunc_v_f32m8_f32m1(op1) __riscv_th_vlmul_trunc_v_f32m8_f32m1(op1)
#define __riscv_vlmul_trunc_v_f32m8_f32m2(op1) __riscv_th_vlmul_trunc_v_f32m8_f32m2(op1)
#define __riscv_vlmul_trunc_v_f32m8_f32m4(op1) __riscv_th_vlmul_trunc_v_f32m8_f32m4(op1)
#define __riscv_vlmul_trunc_v_f64m2_f64m1(op1) __riscv_th_vlmul_trunc_v_f64m2_f64m1(op1)
#define __riscv_vlmul_trunc_v_f64m4_f64m1(op1) __riscv_th_vlmul_trunc_v_f64m4_f64m1(op1)
#define __riscv_vlmul_trunc_v_f64m4_f64m2(op1) __riscv_th_vlmul_trunc_v_f64m4_f64m2(op1)
#define __riscv_vlmul_trunc_v_f64m8_f64m1(op1) __riscv_th_vlmul_trunc_v_f64m8_f64m1(op1)
#define __riscv_vlmul_trunc_v_f64m8_f64m2(op1) __riscv_th_vlmul_trunc_v_f64m8_f64m2(op1)
#define __riscv_vlmul_trunc_v_f64m8_f64m4(op1) __riscv_th_vlmul_trunc_v_f64m8_f64m4(op1)
#define __riscv_vlmul_trunc_v_i8m2_i8m1(op1) __riscv_th_vlmul_trunc_v_i8m2_i8m1(op1)
#define __riscv_vlmul_trunc_v_i8m4_i8m1(op1) __riscv_th_vlmul_trunc_v_i8m4_i8m1(op1)
#define __riscv_vlmul_trunc_v_i8m4_i8m2(op1) __riscv_th_vlmul_trunc_v_i8m4_i8m2(op1)
#define __riscv_vlmul_trunc_v_i8m8_i8m1(op1) __riscv_th_vlmul_trunc_v_i8m8_i8m1(op1)
#define __riscv_vlmul_trunc_v_i8m8_i8m2(op1) __riscv_th_vlmul_trunc_v_i8m8_i8m2(op1)
#define __riscv_vlmul_trunc_v_i8m8_i8m4(op1) __riscv_th_vlmul_trunc_v_i8m8_i8m4(op1)
#define __riscv_vlmul_trunc_v_i16m2_i16m1(op1) __riscv_th_vlmul_trunc_v_i16m2_i16m1(op1)
#define __riscv_vlmul_trunc_v_i16m4_i16m1(op1) __riscv_th_vlmul_trunc_v_i16m4_i16m1(op1)
#define __riscv_vlmul_trunc_v_i16m4_i16m2(op1) __riscv_th_vlmul_trunc_v_i16m4_i16m2(op1)
#define __riscv_vlmul_trunc_v_i16m8_i16m1(op1) __riscv_th_vlmul_trunc_v_i16m8_i16m1(op1)
#define __riscv_vlmul_trunc_v_i16m8_i16m2(op1) __riscv_th_vlmul_trunc_v_i16m8_i16m2(op1)
#define __riscv_vlmul_trunc_v_i16m8_i16m4(op1) __riscv_th_vlmul_trunc_v_i16m8_i16m4(op1)
#define __riscv_vlmul_trunc_v_i32m2_i32m1(op1) __riscv_th_vlmul_trunc_v_i32m2_i32m1(op1)
#define __riscv_vlmul_trunc_v_i32m4_i32m1(op1) __riscv_th_vlmul_trunc_v_i32m4_i32m1(op1)
#define __riscv_vlmul_trunc_v_i32m4_i32m2(op1) __riscv_th_vlmul_trunc_v_i32m4_i32m2(op1)
#define __riscv_vlmul_trunc_v_i32m8_i32m1(op1) __riscv_th_vlmul_trunc_v_i32m8_i32m1(op1)
#define __riscv_vlmul_trunc_v_i32m8_i32m2(op1) __riscv_th_vlmul_trunc_v_i32m8_i32m2(op1)
#define __riscv_vlmul_trunc_v_i32m8_i32m4(op1) __riscv_th_vlmul_trunc_v_i32m8_i32m4(op1)
#define __riscv_vlmul_trunc_v_i64m2_i64m1(op1) __riscv_th_vlmul_trunc_v_i64m2_i64m1(op1)
#define __riscv_vlmul_trunc_v_i64m4_i64m1(op1) __riscv_th_vlmul_trunc_v_i64m4_i64m1(op1)
#define __riscv_vlmul_trunc_v_i64m4_i64m2(op1) __riscv_th_vlmul_trunc_v_i64m4_i64m2(op1)
#define __riscv_vlmul_trunc_v_i64m8_i64m1(op1) __riscv_th_vlmul_trunc_v_i64m8_i64m1(op1)
#define __riscv_vlmul_trunc_v_i64m8_i64m2(op1) __riscv_th_vlmul_trunc_v_i64m8_i64m2(op1)
#define __riscv_vlmul_trunc_v_i64m8_i64m4(op1) __riscv_th_vlmul_trunc_v_i64m8_i64m4(op1)
#define __riscv_vlmul_trunc_v_u8m2_u8m1(op1) __riscv_th_vlmul_trunc_v_u8m2_u8m1(op1)
#define __riscv_vlmul_trunc_v_u8m4_u8m1(op1) __riscv_th_vlmul_trunc_v_u8m4_u8m1(op1)
#define __riscv_vlmul_trunc_v_u8m4_u8m2(op1) __riscv_th_vlmul_trunc_v_u8m4_u8m2(op1)
#define __riscv_vlmul_trunc_v_u8m8_u8m1(op1) __riscv_th_vlmul_trunc_v_u8m8_u8m1(op1)
#define __riscv_vlmul_trunc_v_u8m8_u8m2(op1) __riscv_th_vlmul_trunc_v_u8m8_u8m2(op1)
#define __riscv_vlmul_trunc_v_u8m8_u8m4(op1) __riscv_th_vlmul_trunc_v_u8m8_u8m4(op1)
#define __riscv_vlmul_trunc_v_u16m2_u16m1(op1) __riscv_th_vlmul_trunc_v_u16m2_u16m1(op1)
#define __riscv_vlmul_trunc_v_u16m4_u16m1(op1) __riscv_th_vlmul_trunc_v_u16m4_u16m1(op1)
#define __riscv_vlmul_trunc_v_u16m4_u16m2(op1) __riscv_th_vlmul_trunc_v_u16m4_u16m2(op1)
#define __riscv_vlmul_trunc_v_u16m8_u16m1(op1) __riscv_th_vlmul_trunc_v_u16m8_u16m1(op1)
#define __riscv_vlmul_trunc_v_u16m8_u16m2(op1) __riscv_th_vlmul_trunc_v_u16m8_u16m2(op1)
#define __riscv_vlmul_trunc_v_u16m8_u16m4(op1) __riscv_th_vlmul_trunc_v_u16m8_u16m4(op1)
#define __riscv_vlmul_trunc_v_u32m2_u32m1(op1) __riscv_th_vlmul_trunc_v_u32m2_u32m1(op1)
#define __riscv_vlmul_trunc_v_u32m4_u32m1(op1) __riscv_th_vlmul_trunc_v_u32m4_u32m1(op1)
#define __riscv_vlmul_trunc_v_u32m4_u32m2(op1) __riscv_th_vlmul_trunc_v_u32m4_u32m2(op1)
#define __riscv_vlmul_trunc_v_u32m8_u32m1(op1) __riscv_th_vlmul_trunc_v_u32m8_u32m1(op1)
#define __riscv_vlmul_trunc_v_u32m8_u32m2(op1) __riscv_th_vlmul_trunc_v_u32m8_u32m2(op1)
#define __riscv_vlmul_trunc_v_u32m8_u32m4(op1) __riscv_th_vlmul_trunc_v_u32m8_u32m4(op1)
#define __riscv_vlmul_trunc_v_u64m2_u64m1(op1) __riscv_th_vlmul_trunc_v_u64m2_u64m1(op1)
#define __riscv_vlmul_trunc_v_u64m4_u64m1(op1) __riscv_th_vlmul_trunc_v_u64m4_u64m1(op1)
#define __riscv_vlmul_trunc_v_u64m4_u64m2(op1) __riscv_th_vlmul_trunc_v_u64m4_u64m2(op1)
#define __riscv_vlmul_trunc_v_u64m8_u64m1(op1) __riscv_th_vlmul_trunc_v_u64m8_u64m1(op1)
#define __riscv_vlmul_trunc_v_u64m8_u64m2(op1) __riscv_th_vlmul_trunc_v_u64m8_u64m2(op1)
#define __riscv_vlmul_trunc_v_u64m8_u64m4(op1) __riscv_th_vlmul_trunc_v_u64m8_u64m4(op1)

}] in
def th_vector_misc_wrapper_macros: RVVHeader;
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