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added gr-verilog2 #129

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added gr-verilog2 #129

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@mmaroti mmaroti commented Feb 2, 2025

This module takes a verilog source file and parameter values for the top module and
configures and compiles the module into a loadable dynamic library using verilator.
All of this happens at construction time, so the verilog parameters can be set on
the fly from GRC, and the resulting block can be used as any other gnuradio block.
The verilog code must consume and produce all items using AXI Stream interfaces, and
it can use TDATA, TUSER and TLAST values which are transferred as int32 values.

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