libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688]

We got a response from AMD in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 so the following patch starts treating AMD with AVX and CMPXCHG16B ISAs like Intel by using vmovdqa for atomic load/store in libatomic. We still don't have confirmation from Zhaoxin and VIA (anything else with CPUs featuring AVX and CX16?). 2022-11-15 Jakub Jelinek <[email protected]> PR target/104688 * config/x86/init.c (__libat_feat1_init): Don't clear bit_AVX on AMD CPUs.
gcc-mirror · Nov 15, 2022 · 4a7a846 · 4a7a846
1 parent 7cf165d
commit 4a7a846
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c
@@ -39,10 +39,12 @@ __libat_feat1_init (void)
       == (bit_AVX | bit_CMPXCHG16B))
     {
       /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address
-	 is atomic, but so far we don't have this guarantee from AMD.  */
+	 is atomic, and AMD is going to do something similar soon.
+	 We don't have a guarantee from vendors of other CPUs with AVX,
+	 like Zhaoxin and VIA.  */
       unsigned int ecx2 = 0;
       __get_cpuid (0, &eax, &ebx, &ecx2, &edx);
-      if (ecx2 != signature_INTEL_ecx)
+      if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx)
 	FEAT1_REGISTER &= ~bit_AVX;
     }
 #endif