riscv: remove cache enablement in start.S

Cache could be enabled in harts_early_init board-specific hook, so remove cache enablement in start.S Signed-off-by: Leo Yu-Chi Liang <[email protected]>
frank-w · May 30, 2024 · cea0ed2 · cea0ed2
1 parent ceec476
commit cea0ed2
Showing 1 changed file with 0 additions and 4 deletions.
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@ wait_for_gd_init:
 	bnez	s2, secondary_hart_loop
 #endif
 
-	/* Enable cache */
-	jal	icache_enable
-	jal	dcache_enable
-
 #ifdef CONFIG_DEBUG_UART
 	jal	debug_uart_init
 #endif