Bug 326: Watchdog and Kernel reset should boot to u-boot

Misconfiguration of UART baud-rate hides all u-boot messages. Root Cause: u-boot expects UART clock to be 24MHz, but kernel sets it to be 1.846 MHz. Solution: let kernel not change UART clock, and hard-code baud-rate in DTS. Change-Id: Ieaf01f9be3ac85244b456546ea16f24f8396cf00 Signed-off-by: Wei-Chung Wen <[email protected]>
foxconn-bmc-ks · Sep 7, 2017 · c7fcf03 · c7fcf03
1 parent 845d97f
commit c7fcf03
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Showing 2 changed files with 2 additions and 7 deletions.
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-g50.dts b/arch/arm/boot/dts/aspeed-bmc-opp-g50.dts
@@ -13,7 +13,7 @@
 
 	chosen {
 		stdout-path = &uart5;
-		bootargs = "console=ttyS4,38400 earlyprintk";
+		bootargs = "console=ttyS4,115200 earlyprintk";
 	};
 
 	memory {
@@ -68,6 +68,7 @@
 
 &uart5 {
 	status = "okay";
+	current-speed = <115200>;
 };
 
 &i2c0{

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
@@ -141,12 +141,6 @@ static void __init do_sthelens_setup(void)
 
         /* SCU config */
         writel(0x10CC5E80, AST_IO(AST_BASE_SCU | 0x0c));
-        /* We enable the UART clock divisor in the SCU's misc control
-         * register, as the baud rates in aspeed.dtb all assume that the
-         * divisor is active
-         */
-        reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
-        writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));
 
         //Disable host SPI mode  bit 12:13 = 00
         writel(0xFA1C84D6, AST_IO(AST_BASE_SCU | 0x70));