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Implicit ignore unsupported syscalls #52

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merged 5 commits into from
Apr 16, 2024
Merged

Implicit ignore unsupported syscalls #52

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bb572ed
Ignore unrecognized syscalls implicitly
ImTei Apr 16, 2024
4e45a4e
Check if preimage process is terminated
ImTei Apr 16, 2024
93d5cf5
Return 0 for unsupported syscalls
ImTei Apr 16, 2024
593801a
Add comments for Guard()
ImTei Apr 16, 2024
76ea1c5
Update contract binding
ImTei Apr 16, 2024
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2 changes: 1 addition & 1 deletion rvgo/bindings/preimageoracle.go
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2 changes: 1 addition & 1 deletion rvgo/bindings/preimageoracle_more.go
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2 changes: 1 addition & 1 deletion rvgo/bindings/riscv.go
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2 changes: 1 addition & 1 deletion rvgo/bindings/riscv_more.go
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4 changes: 3 additions & 1 deletion rvgo/cmd/run.go
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Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,13 @@ type Proof struct {

type StepFn func(proof bool) (*fast.StepWitness, error)

// Guard checks if the step is failed due to pre-image server error
func Guard(proc *os.ProcessState, fn StepFn) StepFn {
return func(proof bool) (*fast.StepWitness, error) {
wit, err := fn(proof)
if err != nil {
if proc.Exited() {
// proc is not nil when the preimage server process is terminated
if proc != nil && proc.Exited() {
return nil, fmt.Errorf("pre-image server exited with code %d, resulting in err %w", proc.ExitCode(), err)
} else {
return nil, err
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58 changes: 12 additions & 46 deletions rvgo/fast/vm.go
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Original file line number Diff line number Diff line change
Expand Up @@ -515,31 +515,13 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
case riscv.SysOpenat: // openat - the Go linux runtime will try to open optional /sys/kernel files for performance hints
setRegister(toU64(10), u64Mask())
setRegister(toU64(11), toU64(0xd)) // EACCES - no access allowed
case riscv.SysSchedGetaffinity: // sched_getaffinity - hardcode to indicate affinity with any cpu-set mask
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysSchedYield: // sched_yield - nothing to yield, synchronous execution only, for now
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysClockGettime: // clock_gettime
addr := getRegister(toU64(11)) // addr of timespec struct
// write 1337s + 42ns as time
value := or(shortToU256(1337), shl(shortToU256(64), toU256(42)))
storeMemUnaligned(addr, toU64(16), value, 1, 2, true, true)
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysRtSigprocmask: // rt_sigprocmask - ignore any sigset changes
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysSigaltstack: // sigaltstack - ignore any hints of an alternative signal receiving stack addr
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysGettid: // gettid - hardcode to 0
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysRtSigaction: // rt_sigaction - no-op, we never send signals, and thus need no sig handler info
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysClone: // clone - not supported
setRegister(toU64(10), toU64(1))
setRegister(toU64(11), toU64(0))
Expand All @@ -556,41 +538,25 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
default:
revertWithCode(riscv.ErrUnrecognizedResource, &UnrecognizedResourceErr{Resource: res})
}
case riscv.SysMadvise: // madvise - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysEpollCreate1: // epoll_create1 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysEpollCtl: // epoll_ctl - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysPipe2: // pipe2 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysReadlinnkat: // readlinkat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysNewfstatat: // newfstatat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysNewuname: // newuname - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysMunmap: // munmap - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysGetRandom: // getrandom - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysPrlimit64: // prlimit64 -- unsupported, we have getrlimit, is prlimit64 even called?
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
case riscv.SysFutex: // futex - not supported, for now
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
case riscv.SysNanosleep: // nanosleep - not supported, for now
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
default:
revertWithCode(riscv.ErrInvalidSyscall, &UnrecognizedSyscallErr{SyscallNum: a7})
// Ignore(no-op) unsupported system calls
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
// List of ignored(no-op) syscalls used by op-program:
// sched_getaffinity - hardcode to indicate affinity with any cpu-set mask
// sched_yield - nothing to yield, synchronous execution only, for now
// rt_sigprocmask - ignore any sigset changes
// sigaltstack - ignore any hints of an alternative signal receiving stack addr
// gettid - hardcode to 0
// rt_sigaction - no-op, we never send signals, and thus need no sig handler info
// madvise, epoll_create1, epoll_ctl, pipe2, readlinkat, newfstatat, newuname, munmap,
// getrandom, ioctl, getcwd, getuid, getgid
}
}

Expand Down
49 changes: 3 additions & 46 deletions rvgo/slow/vm.go
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Original file line number Diff line number Diff line change
Expand Up @@ -695,31 +695,13 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
case riscv.SysOpenat: // openat - the Go linux runtime will try to open optional /sys/kernel files for performance hints
setRegister(toU64(10), u64Mask())
setRegister(toU64(11), toU64(0xd)) // EACCES - no access allowed
case riscv.SysSchedGetaffinity: // sched_getaffinity - hardcode to indicate affinity with any cpu-set mask
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysSchedYield: // sched_yield - nothing to yield, synchronous execution only, for now
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysClockGettime: // clock_gettime
addr := getRegister(toU64(11)) // addr of timespec struct
// write 1337s + 42ns as time
value := or(shortToU256(1337), shl(shortToU256(64), toU256(42)))
storeMemUnaligned(addr, toU64(16), value, 1, 2)
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysRtSigprocmask: // rt_sigprocmask - ignore any sigset changes
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysSigaltstack: // sigaltstack - ignore any hints of an alternative signal receiving stack addr
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysGettid: // gettid - hardcode to 0
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysRtSigaction: // rt_sigaction - no-op, we never send signals, and thus need no sig handler info
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysClone: // clone - not supported
setRegister(toU64(10), toU64(1))
setRegister(toU64(11), toU64(0))
Expand All @@ -736,41 +718,16 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
default:
revertWithCode(riscv.ErrUnrecognizedResource, &UnrecognizedResourceErr{Resource: res})
}
case riscv.SysMadvise: // madvise - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysEpollCreate1: // epoll_create1 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysEpollCtl: // epoll_ctl - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysPipe2: // pipe2 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysReadlinnkat: // readlinkat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysNewfstatat: // newfstatat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysNewuname: // newuname - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysMunmap: // munmap - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysGetRandom: // getrandom - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
case riscv.SysPrlimit64: // prlimit64 -- unsupported, we have getrlimit, is prlimit64 even called?
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
case riscv.SysFutex: // futex - not supported, for now
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
case riscv.SysNanosleep: // nanosleep - not supported, for now
revertWithCode(riscv.ErrInvalidSyscall, &UnsupportedSyscallErr{SyscallNum: a7})
default:
revertWithCode(riscv.ErrInvalidSyscall, &UnrecognizedSyscallErr{SyscallNum: a7})
// Ignore(no-op) unsupported system calls
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
}

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81 changes: 5 additions & 76 deletions rvsol/src/RISCV.sol
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Original file line number Diff line number Diff line change
Expand Up @@ -1043,16 +1043,6 @@ contract RISCV {
setRegister(toU64(10), u64Mask())
setRegister(toU64(11), toU64(0xd)) // EACCES - no access allowed
}
case 123 {
// sched_getaffinity - hardcode to indicate affinity with any cpu-set mask
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 124 {
// sched_yield - nothing to yield, synchronous execution only, for now
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 113 {
// clock_gettime
let addr := getRegister(toU64(11)) // addr of timespec struct
Expand All @@ -1062,26 +1052,6 @@ contract RISCV {
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 135 {
// rt_sigprocmask - ignore any sigset changes
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 132 {
// sigaltstack - ignore any hints of an alternative signal receiving stack addr
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 178 {
// gettid - hardcode to 0
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 134 {
// rt_sigaction - no-op, we never send signals, and thus need no sig handler info
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 220 {
// clone - not supported
setRegister(toU64(10), toU64(1))
Expand All @@ -1104,51 +1074,6 @@ contract RISCV {
}
default { revertWithCode(0xf0012) } // unrecognized resource limit lookup
}
case 233 {
// madvise - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 20 {
// epoll_create1 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 21 {
// epoll_ctl - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 59 {
// pipe2 - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 78 {
// readlinkat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 79 {
// newfstatat - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 160 {
// newuname - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 215 {
// munmap - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 278 {
// getrandom - ignored
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
case 261 {
// prlimit64 -- unsupported, we have getrlimit, is prlimit64 even called?
revertWithCode(0xf001ca11) // unsupported system call
Expand All @@ -1161,7 +1086,11 @@ contract RISCV {
// nanosleep - not supported, for now
revertWithCode(0xf001ca11) // unsupported system call
}
default { revertWithCode(0xf001ca11) } // unrecognized system call
default {
// Ignore(no-op) unsupported system calls
setRegister(toU64(10), toU64(0))
setRegister(toU64(11), toU64(0))
}
}

//
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11 changes: 0 additions & 11 deletions rvsol/test/RISCV.t.sol
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Original file line number Diff line number Diff line change
Expand Up @@ -2390,17 +2390,6 @@ contract RISCV_Test is CommonTest {
riscv.step(encodedState, proof, 0);
}

function test_unrecognized_syscall() public {
uint16 imm = 0x0;
uint32 insn = encodeIType(0x73, 0, 0, 0, imm); // ecall
(State memory state, bytes memory proof) = constructRISCVState(0, insn);
state.registers[17] = 999; // unrecognized syscall
bytes memory encodedState = encodeState(state);

vm.expectRevert(hex"00000000000000000000000000000000000000000000000000000000f001ca11");
riscv.step(encodedState, proof, 0);
}

function test_invalid_amo_size() public {
uint32 insn;
uint8 funct3 = 0x1; // invalid amo size
Expand Down
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